The System Manual of SOL-20 - History of Computers
The System Manual of SOL-20 - History of Computers
The System Manual of SOL-20 - History of Computers
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PROCESSOR TECHNOLOGY CORPORATION<br />
Sol THEORY OF OPERATION<br />
SECTION VIII<br />
set to the outputs <strong>of</strong> latches U2 and 13. U2 latches the starting row<br />
address from DIO0-3 and U13 latches the data on DIO4-7, with<br />
!PORT_OUT_FE being the strobe. Data on DIO4-7 specifies where the<br />
first line will be displayed. Thus, the number loaded into U1 is<br />
the address <strong>of</strong> the first displayable scan line, and the number loaded<br />
into U22 defines the character row (0 through 15).<br />
U11 is preset by !VDISP from pin 9 <strong>of</strong> J-!K flip-flop U43. This<br />
means U11 is forced to its preset condition from the end <strong>of</strong> the displayed<br />
text to the top <strong>of</strong> the next character row. During this time,<br />
pin 6 <strong>of</strong> another U43 J-!K flip-flop is set high to preset U1. If U11<br />
is preset to 0, its TC output on pin 7 is low and pin 6 <strong>of</strong> U43 is reset<br />
to a low. This allows U1 to count with each horizontal scan line.<br />
If U11 is preset to any number other than 0, pin 6 <strong>of</strong> U43 cannot<br />
be reset low until U11 reaches zero. Assume U11 is preset to<br />
two. It must count down two character rows before U1 starts counting.<br />
During this time, pin 7 <strong>of</strong> U43 (PRE_BLANK) is low, and as previously<br />
discussed, the display is blanked.<br />
We can now see that the PRE_BLANK time, <strong>of</strong>ten called "window<br />
shade", is variable with the number loaded into U11. <strong>The</strong>refore,<br />
scrolling is performed by changing the numbers in U2 and U13 without<br />
the need to reposition the text within the Display RAM.<br />
<strong>The</strong> remaining circuit in the Display Section consists <strong>of</strong><br />
transistor Q2, one section <strong>of</strong> U87, 89 and 102. U88 and U102 are connected<br />
as a one-shot 250 msec timer that is triggered when<br />
!PORT_OUT_FE goes active (pin 1 <strong>of</strong> inverter U87 goes high). Thus,<br />
when data is loaded into U2 and U13, this timer starts. Tri-state<br />
driver U89, which is enabled by !PORT_IN_FE, transmits the state <strong>of</strong><br />
this timer to D100 on the Bidirectional Data Bus. <strong>The</strong> CPU can consequently<br />
test the timer status by looking for a high on DIO0. This<br />
timing allows a 250 msec scroll rate without the need for complex<br />
timing routines in the CPU. Q2, R102 and C37 serve to speed up timer<br />
reset.<br />
8.5.5 Audio Tape I/O<br />
Refer to Audio Tape I/O Schematic in Section X, Page X-19.<br />
Timing for the Audio Tape I/O is derived from the 1<strong>20</strong>0, 2400,<br />
4800, 19,<strong>20</strong>0 and 38,400 Hz signals received from the Baud Rate Generator<br />
in the Input/Output section <strong>of</strong> Sol. <strong>The</strong> first two are used by<br />
the write data synchronizer (U100) and the digital-to-audio converter<br />
(U101).<br />
<strong>The</strong> remaining three signals are fed to two sections <strong>of</strong> U111,<br />
a quad multiplexer or select gate. All four sections <strong>of</strong> U111 are<br />
used to select clocks for low speed or high speed operation according<br />
to the select inputs, pins 9 (A) and 14 (B). <strong>The</strong> states <strong>of</strong> these two<br />
select inputs must be complementary to each other in order to select<br />
VIII-33