The System Manual of SOL-20 - History of Computers

PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
SECTION VIII
U100. The output on pin 12 of U100 is inverted by U109 and applied
to the receive input (pin 20) of the UART.
The Q output on pin 1 of U113, which occurs at the actual bit
rate of the incoming data, is also used by the receive clock circuitry
to reconstruct the receive clock from the data signal.
Received data undergoes serial-to-parallel conversion in the
UART and is placed on the RO1-8 data outputs of the UART when ROD
(pin 4 of the UART) is low (!PORT_IN_FB active) and onto INT0-7.
Four status outputs from the UART can also be enabled when
SFD (pin 16) is low. These four bits are FE (framing error), OE
(overrun error), DR (data ready) and TBRE (transmitter buffer register
empty).
8.6 KEYBOARD
8.6.1 Block Diagram Analysis
A simplified block diagram of the keyboard is provided on
Page X-25 in Section X.
The Clock Oscillator produces the basic timing signals for
the keyboard, and they are distributed as indicated.
At the heart of the keyboard is a Key Switch Capacitive
Matrix which can be viewed as a 16 x 16 X-Y matrix, with X being the
column and Y the row. Conceptually, a key depression increases the capacitance
between the X and Y coordinates that uniquely define that
key.
The Column Scanner supplies a pulse train to the X lines in
the matrix, with only one line being pulsed at any given point in
time. When a key is depressed to increase the capacitance between the
Column Scanner output and a Row Scanner input, the X-Y coordinates
for that key are detected to provide an input to the Sense Circuit.
The Sense Circuit in turn generates an input to the Sequence
Detector when a key closure occurs. This detector basically detects
key closures and count cycles of the Row Scanner to discriminate
against false key signals and insure that valid closures are serviced
in order.
In the absence of key closures, the Sequence Detector feeds
PKD to the Sense Circuit to increase its threshold. This action
serves to increase the circuit's noise immunity. On valid key closures,
the PKD input is such as to decrease the Sense Circuit's
threshold. When valid key closures exist, the Sequence Detector
strobes data into the Output Latch. The low order four bits to this
latch are supplied by the Row Scanner; the high order four bits are
VIII-38