The System Manual of SOL-20 - History of Computers

PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
SECTION VIII
Output data from the CPU that is channeled through the Parallel
Port (PP) is latched from the Bidirectional Data Bus by the parallel
strobe from the Address Page and I/O Port Decoder. This data
is made available at P2, the PP connector. Parallel input data
(PID0-7) on P2, however, is fed directly to the Data Input Multiplexer
for entry into the CPU.
As can be seen, keyboard data (KBD0-7) from J3 is also fed
directly to the Data Input Multiplexer. The keyboard data ready
flag, though, is input to the CPU on the internal data bus.
The remaining internal source of data input to the CPU is
the Sense Switch Logic, with the data being input on the Bidirectional
Data Bus. This is an eight-switch Dual Inline Package (DIP)
array that lets the CPU read an eight-bit word when it issues the
sense switch strobe via the Address Page and I/O Port Decoder. The
sense switch data source is available to interact with the user's
software.
CPU Support Logic accepts six control outputs from the CPU,
status information from the CPU's data bus and control signals from
the Control Bus. It controls traffic on the data buses by generating
signals to 1) select the type of internal or external device
(memory or I/O) that will have bus access and 2) assure that the device
properly transfers data with the CPU.
8.3.2 Typical System Operation
Basic Sol system operation is as follows: The CPU fetches
an instruction and in accordance with that instruction issues an
activity command on the Control Bus, outputs a binary code on the
Address Bus to identify the memory location or I/O device that is to
be involved in the activity, sends or receives data on the data bus
with the selected memory location or I/O device, and upon completion
of the activity issues the next activity command.
Let's now look at some typical operating sequences.
Keyboard Data Entry and Display. Assume the "A" and SHIFT
keys on the keyboard are pressed. The keyboard circuitry converts
the key closures into the 7-bit ASCII (American Standard Code for
Information Interchange) code for an "A" {1000001) and sends a keyboard-data-ready
status signal to the CPU on the Internal Data Bus.
The monitor program in ROM repetitively "looks" for the status
signal. When it finds this signal the program enters its keyboard
routine and enables the transfer by switching the Data Input Multiplexer
to the keyboard bus via the Address Page and I/O Port Decoder.
Following program instructions, the CPU addresses the Display
RAM on the Address Bus to determine where the next character is to
appear on the screen. It then stores the ASCII code for the "A" at
the appropriate location in the Display RAM and adds one to the cursor
position in readiness for the next character. (Addressing is
VIII-5