The System Manual of SOL-20 - History of Computers

PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
SECTION VIII
supplied by the Encoding ROM, with the data being determined by inputs
from the Column Scanner and Function Latch Decoder. This
strobe (Data Out) also enables the Strobe Generator to output !STROBE
a 6 usec pulse that signals the Sol CPU that the Keyboard is ready to
send data.
Eight bits of keyboard data (KBD0 through KBD7) are stored in
the Output Latch. KBD0 through KBD6 represent the ASCII code for the
character associated with the key closure, or closures, that initiated
the Data Out strobe from the Sequence Detector. KBD7 is used
only for special control characters (e.g. MODE SELECT, CLEAR and cursor
movement) that are recognized by the Sol program. The data on
KBD0-7 is input to the Sol CPU when it issues !PORT_IN_FC (refer to
Paragraph 8.5.2 on Page VIII-14).
The Repeat Counter is enabled when the REPEAT key and a character
key in the Key Switch Capacitive Matrix are pressed at the same
time. When this occurs, Key Out (initiated by the character key closure)
is active, and the Repeat Counter generates a periodic Repeat
Strobe. This strobe disables the Sequence Detector and causes the
Strobe Generator to output repetitive !STROBE pulses. Column 30 also
prevents the Sequence Detector from strobing additional data into the
Output Latch.
The Function Latch and Decoder latches and decodes the Low
Order Count from the Row Scanner when the "function key" column in
the Switch Matrix is selected by the Column Scanner. It then outputs,
as appropriate, !LOCAL, !RST and !BRK to J1 and SHIFT/SHIFT_LOCK, UPPER_
CASE and CONTROL bits to the Encoding ROM. The latter three supply
three of the seven address bits to the ROM which specify the high
order four KBD bits (KBD4-7).
All keyboard outputs are supplied to J1 which is connected
to J3 on the Sol-PC.
8.6.2 Circuit Description
Refer to the Keyboard schematic in Section X, Page X-23.
Keyboard operation is controlled by a 3 usec clock circuit
consisting of NAND gate U7, R7 and C7. U7 is connected as a Schmitt
trigger inverter with negative feedback through R7 and C7. The output
on pin 11 of U7, a square wave with a 3 usec period, is inverted
in U4 (a NAND gate connected as a simple inverter) and applied to the
clock input (pin 11) of U8. U8 operates in a toggle mode by virtue
of feeding its !Q output on pin 8 to the D input on pin 12. Thus, its
output state changes on each clock to produce a 6 usec and an inverted
6 usec clock on pins 9 and 8 respectively.
Each of these outputs is connected to a section of U7 where
each is AND'ed with the 3 usec clock. This generates two negative
going clocks at pins 8 and 6 of U7. These outputs are called !φ1 and
VIII-39