The System Manual of SOL-20 - History of Computers
The System Manual of SOL-20 - History of Computers
The System Manual of SOL-20 - History of Computers
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PROCESSOR TECHNOLOGY CORPORATION<br />
Sol THEORY OF OPERATION<br />
SECTION VIII<br />
interrupt operation. To prevent this, SINTA is inverted in U58 to 1)<br />
disable U34 on pin 6 and 2) force pin 8 <strong>of</strong> NAND gate U23 high to disable<br />
U35 and U36 on pin 5. (This feature is provided to enable future<br />
versions <strong>of</strong> Sol to operate with a vectored interrupt system.)<br />
8.5.3 Input/Output<br />
Refer to the Input/Output Schematic In Section X, Page X-17.<br />
This section in the Sol has five functional circuits: 1)<br />
Parallel I/O Logic, 2) Sense Switch Logic, 3) Keyboard Flag Logic,<br />
4) SDI/UART and 5) Baud Rate Generator.<br />
<strong>The</strong> PP uses U95 and 96 (4-bit D-type registers) and their related<br />
logic. Data output to the PP connector (J2) is latched from<br />
DIO0-7 by U95 and U96. Data is strobed into these registers on the<br />
leading edge <strong>of</strong> an inverted active !PORT_OUT_FD signal on pin 4 <strong>of</strong> inverter<br />
U54. This strobe is also applied to pin 2 <strong>of</strong> U73 which functions<br />
as a J-K flip-flop that is clocked by !φ2. When the !φ2 goes<br />
from low to high <strong>20</strong>0 to 300 nsec after !PORT_OUT_FD, pin 7 <strong>of</strong> U73 goes<br />
low to become !POL on pin 17 <strong>of</strong> J2. (This delay allows U95 and 96 to<br />
stabilize.) U73 is reset in the middle <strong>of</strong> the following PSYNC which<br />
means !P0L is active for the balance <strong>of</strong> the cycle.<br />
<strong>The</strong> outputs <strong>of</strong> U95 and 96 are tri-state outputs that are enabled<br />
by a low on pin 2. In the absence <strong>of</strong> POE at pin 15 <strong>of</strong> J2, pin 2<br />
<strong>of</strong> U95 and 96 are low by virtue <strong>of</strong> the output on pin 8 <strong>of</strong> inverter U55.<br />
Note that the input to U55 is normally pulled up through R63. <strong>The</strong> POE<br />
provision permits tri-stating an external bidirectional data bus.<br />
As discussed in Paragraph 8.5.1, parallel input data on J2 is<br />
fed directly to the Data Input Multiplexer (see Page X-15). <strong>The</strong><br />
strobe that indicates the presence <strong>of</strong> input data, !PDR on pin 4 <strong>of</strong> J2,<br />
is applied to pins 2 and 3 <strong>of</strong> one section in U72, a J-!K flip-flop<br />
which is connected as a D flip-flop. When !PDR goes active (low), pin<br />
7 <strong>of</strong> U72 will go high on the next low-to-high transition <strong>of</strong> φ2 to<br />
toggle the following U72 stage. At this point pins 9 and 10 <strong>of</strong> the<br />
second section in U72 go high and low respectively. Pin 9 supplies<br />
PIAK on pin 5 <strong>of</strong> J2. When high, PIAK signals the external device<br />
that Sol has yet to complete acceptance <strong>of</strong> the data. <strong>The</strong> state <strong>of</strong><br />
pin 10 <strong>of</strong> U72 is transmitted to INT1 <strong>of</strong> the Internal Data Bus through<br />
a U71 tri-state noninverting buffer. U71 is enabled only for the<br />
duration <strong>of</strong> !PORT_IN_FA (auxiliary status). During the time U71 is<br />
enabled, the CPU reads the Internal Data Bus. A high INT1 indicates<br />
the parallel input data is not ready; a low indicates the data is<br />
ready.<br />
<strong>The</strong> second U72 flip-flop is preset by !PORT_IN_FD or POC.<br />
!PORT_IN_FD is active to read data in from the PP; POC occurs only<br />
when Sol is restarted or power is turned on. Thus the PP is reset<br />
and ready for another transfer at the end <strong>of</strong> a transfer or when POC<br />
is active.<br />
VIII-18