The System Manual of SOL-20 - History of Computers
The System Manual of SOL-20 - History of Computers
The System Manual of SOL-20 - History of Computers
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PROCESSOR TECHNOLOGY CORPORATION<br />
Sol THEORY OF OPERATION<br />
SECTION VIII<br />
the high or low speed clocks. Specifically, A must be high and B low<br />
to select high speed clocks; the converse condition selects low speed<br />
clocks. <strong>The</strong> select inputs are supplied by TAPE_HI_SPEED and<br />
!TAPE_HI_SPEED.<br />
<strong>The</strong> output <strong>of</strong> the second section on pin 11 <strong>of</strong> U111 is BYTE_<br />
WRITE_CLOCK, 4800 Hz on low speed and 19.2 KHz on high speed. <strong>The</strong><br />
third section outputs a 19.2 KHz (high speed) or 38.4 KHz (low speed)<br />
timing signal to input pin 10 <strong>of</strong> binary up counter (U112).<br />
RECOVER_CLOCK is produced by a phase locked loop (U110), another<br />
U112 binary up counter and the first and fourth sections <strong>of</strong> U111.<br />
<strong>The</strong> signal input (pin 14) to U110 is supplied from output pin 1 <strong>of</strong> D<br />
flip-flop U113. It is a constant frequency, regardless <strong>of</strong> whether<br />
one or two transitions are detected in the read data during the<br />
count out time (12 counts) <strong>of</strong> the U112 counter with outputs on pins<br />
13 and 14. A phase comparator in U110 compares the signal input to<br />
the output <strong>of</strong> a voltage controlled oscillator (VCO) in U110 (pin 4).<br />
By feeding the VCO output through a counter (the other half <strong>of</strong> U112)<br />
before feeding the counter output back to the compare input (pin 3)<br />
<strong>of</strong> U110, the circuit acts as a frequency multiplier. <strong>The</strong> output <strong>of</strong><br />
this circuit remains locked, therefore, to a multiple <strong>of</strong> the signal<br />
input on pin 14 <strong>of</strong> U110.<br />
<strong>The</strong> output <strong>of</strong> U110 is nominally 19.2 KHz. <strong>The</strong> actual output<br />
is determined by the signal input which in turn is a function <strong>of</strong> tape<br />
speed. In other words, the phase lock loop circuit tracks input frequency<br />
variations. And it will track such variations within its<br />
locking range which is determined by the setting <strong>of</strong> variable resistor<br />
VR3 (connected to pin 12 <strong>of</strong> U110).<br />
For high speed, the divide-by-four output <strong>of</strong> U112 (pin 4) is<br />
selected as RECOVER_CLOCK. For low speed, the VCO output <strong>of</strong> U110 is<br />
selected for RECOVER_CLOCK. This clock serves as read clock for the<br />
CDI UART, U69.<br />
CDI control involves !PORT_IN_FA, !PORT_IN_FB, !PORT_OUT_FB,<br />
TAPE_CONTROL_1 and _2, POC (power on clear), TAPE_HIGH_SPEED and<br />
!TAPE_HI_SPEED. <strong>The</strong> last two were previously explained in the discussion<br />
<strong>of</strong> U111. !PORT_IN_FA strobes the CDI UART status (DR, TBRE,<br />
OE and FE--refer to Page VIII-22 for definitions) to the Internal<br />
Data Bus, INT3-7. !PORT_IN_FB strobes received data on pins 5-12 <strong>of</strong><br />
U69 to the Internal Data Bus, INT0-7. !PORT_OUT_FB loads data from<br />
the Bidirectional Data Bus (DIO0-7) into U69. POC simply resets<br />
U69 whenever power is applied to the Sol.<br />
TAPE_CONTROL_1 and _2 are used to turn one or two recorder<br />
motors on and <strong>of</strong>f. An active low TAPE_CONTROL_1 energizes K1 to<br />
close its contacts and turn recorder #l on; a high de-energizes K1 to<br />
turn the recorder <strong>of</strong>f. TAPE_CONTROL_2 does the same thing with K2 to<br />
control another recorder. Diodes D13 and 14, which shunt K1 and K2<br />
VIII-34