Direct Power and Torque Control of AC/DC/AC Converter-Fed ...

5. Passive Components Design
dU
C
dt
C
dc
= Idc
− Iload
= ∑ ILk
k = A
S
k
− I
load
≈ I
LA
S
A
+ I
LB
S
B
+ I
LC
S
C
P
−
U
(5. 2)
For given allowable peak ripple voltage and switching frequency, the minimum
capacitor for the converter in Fig.4. 1 can be found from [24]:
C
min_VSR1
3U
LL
2 +
Udc
= Pload
_ max
,
(5. 3)
2 3∆U
f U
dc
s
LL
load
dc
Where:
U
LL
- is a line to line voltage,
load _ max
P - maximal load power, ∆U
dc
-
specified peak to peak voltage ripple in DC-link during steady states.
Another approach of the DC-link capacitors design, takes into account following
considerations:
• the voltage ripple, due to the high-frequency components of the modulated
DC- link currents of both converters (i.e. VSR and VSI), have to remain
within desired limits,
• when all switches of VSR are off, the inductors energy flows into the
capacitor, increasing its voltage,
• the capacitor energy has to sustain the output power demand in a period of
the time delay of the DC-link voltage control loop.
The first and the second point of considerations are less important, while the third
one practically determines the capacitor value. Assuming time delay of the DC-link
voltage control loop T UT
and variation of the maximal load power ∆ P load _ max , the
energy exchanged by the DC-link capacitor can be estimated as:
∆ W = ∆P T
(5. 4)
dc
load _ max
Where, T
UT
is defined in Section 3.3.3.2.
UT
From this equation the maximal DC-link voltage variation during transient is
expressed by:
∆W
dc
∆ U
dc _ max
= (5. 5)
Cmin_VSR2U
dc
Considering the maximal voltage variation during transient
rearrange an Eq. (5.5) the minimal capacitance can be calculated as [90]:
∆ U dc _ max and
98