DevKit8500D/A User Manual - DMCS Pages for Students
DevKit8500D/A User Manual - DMCS Pages for Students
DevKit8500D/A User Manual - DMCS Pages for Students
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Chapter 2 Hardware System<br />
2.1 CPU<br />
2.1.1 CPU Introduction<br />
As a high-per<strong>for</strong>mance processor <strong>for</strong> enhanced digital media, DM37x/AM37x employs TI 45nm<br />
advanced industrial technology; this architecture has the advantage of low power consumption at<br />
the same time of being designed <strong>for</strong> ARM and graphical demonstration.<br />
The Texas Instruments’ DM3730 DaVinci digital media processor is powered by up to 1-GHz<br />
(also supports 300, 600, and 800-MHz operation) ARM Cortex-A8 and 800-MHz (also supports<br />
250, 520 and 660-MHz operation) C64x+ DSP core, and has integrated 3D graphics processor,<br />
imaging and video accelerator (IVA), USB 2.0, MMC/SD memory card, UART and many more.<br />
DaVinci DM3730 video processor is pin-to-pin compatible with Sitara AM37x devices and software<br />
compatible with the OMAP35x processors. The C64x+ DSP and hardware video accelerator<br />
enable audio and HD 720p video decoding and encoding independent of the ARM processor. The<br />
programmable DSP engine allows multiple signal processing tasks such as image processing and<br />
analysis, digital filtering, and math functions. DaVinci DM3730 video processor is suitable <strong>for</strong> 720p<br />
HD (High Definition) video applications which require large amount of data processing.<br />
2.1.2 CPU Features<br />
Clock<br />
The CPU clock includes sys_32k, sys_altclk, sys_clkout1, sys_clkout2, sys_xtalout, sys_xtalin,<br />
sys_clkreq.<br />
The sys_32k 32-kHz clock is used <strong>for</strong> low frequency operation. It supplies the wake-up domain<br />
signals <strong>for</strong> operating in lowest power mode (off mode). This clock is provided through the sys_32k<br />
pin. The 32-kHz is generated by power management.<br />
The sys_xtalin / sys_xtalout system input clock (26 MHz) is used to generate the main source<br />
clock <strong>for</strong> the device. It supplies the DPLLs as well to several other modules.<br />
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