Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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Intel ® GW80314 I/O Processor DMA and XOR LibraryLibrary Functional Overview2.0 Library Functional OverviewThe Intel ® GW80314 I/O processor features includes DMA/XOR Block and an Intel ® XScale core. One of the important features of the Intel ® XScale core is the ability to customize cachepolicy by memory page.The base DMA/XOR GW80314 Library provides a hardware interface/memory map:• DMA/XOR Block.• Intel ® XScale Microarchitecture.The complete Library solution provides:• Integrated descriptor handling (one set of APIs) for DMA/XOR on four channels:— pre-runtime allocation/alignment of XOR/ DMA buffers (descriptors).— Descriptor Free Stacks and Post Queues.— Free descriptors by pointer allocation.— Descriptor reclamation from descriptor chain.• Customized cache policy for descriptor processing and data memory regions.• Interrupt controller setup for DMA and XOR transactions including chaining in of interrupthandlers.• Library Demos: Present full implementation of the DMA/XOR Library functionality.2.1 Library Usage ModelsThe DMA/XOR Library is flexible and can be:• Implemented as a turnkey solution.• Used cafeteria style with any or all components, code, methodologies and documentreferences.10 APIs and Testbench White Paper
Intel ® GW80314 I/O Processor DMA and XOR LibraryIntel ® GW80314 I/O Processor Component Overview3.0 Intel ® GW80314 I/O Processor Component OverviewThis section provides an overview of the DMA/XOR Controller and the Intel ® XScale core andTransaction Data Paths.3.1 Data Paths and Components3.1.1 FunctionFigure 1 provides an overview of the GW80314 with the data paths and DMA/XOR relevantcomponents: XOR Controller, DMA Controller and Intel ® XScale core. Here is a description of dataflow.• Intel ® XScale microarchitecture Descriptor Processing:— Code is run from SDRAM by the Intel ® XScale microarchitecture using the standardfetch, decode and execute model.— Descriptors are written to SDRAM or SRAM.— Memory mapped DMA/XOR registers are written to initiate transaction. DMA or XORcontroller, using the pointer to memory, reads the descriptor values from RAM into DMA orXOR Controller registers. Based on descriptor values, the DMA/XOR Controller beginsexecution.• DMA/XOR Controller Operations.— For a XOR or DMA transfer: the data is transferred first into the DMA/XOR block andthen transferred to destination.In terms of software descriptor processing optimization, the primary goal is to minimize traffic on thebus. The programmer can support this objective by minimizing traffic for descriptor processing betweenSDRAM/SRAM and the Intel ® XScale core. The bus transactions created by the DMA/XOR blockare handled by the controllers.The GW80314 is designed as a fabric centric, any port-to-any port bridge. All transactions areplaced into fabric packets and routed through address based port selection to another fabric port.The bridge is based on the ‘store and forward’ concept where transactions are buffered at theincoming port. When a packet is complete the incoming port knows the size of the packet, and itmay be burst across the fabric to the outgoing port. As the timing of the packet is deterministic atthe outgoing port, the transaction may be started at the outgoing port as soon as the header arrives.All outgoing ports have the capability to buffer incoming packets to allow for delayed access to theexternal bus.The internal packets are limited to 256 bytes in size in order to limit the latency and to provide acertain quality of service. Larger PCI transactions are broken into 256 byte transactions at the PCIport.APIs and Testbench White Paper 11
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