Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

Intel ® GW80314 I/O Processor DMA and XOR LibraryIntel ® GW80314 I/O Processor Component Overview• Mode selectable byte/word conversion on transferred data• Ability to launch DMA or XOR operation from a single write transaction• Calculate CRC on the DMA transferred data based on the CRC-32C algorithm required by theiSCSI Specification• Pipelines read requests or read and write requests for better performance• Go/stop/halt control of data transfer operationFigure 3.DMA/XOR ChannelAHB RegistersDirect_FillXOR Store QueueXOR ControlRegister UpdateControls64-Bit Data Path256 Byte Accumulator32-Bit CRCFSMCRC GeneratorCRCControlPacketData Out64-Bit Data Path32-Bit CRCSFN Packet InPacketHeaderInfo OutB1971-013.2.3 Memory: SRAM and SDRAMFor DMA/XOR Descriptor processing both SRAM and SDRAM can be used. Both are mapped tocache and both can be set of any of the XScale Data Cache Policies.3.3 Intel ® XScale Microarchitecture3.3.1 OverviewThe Intel ® XScale microarchitecture (compliant with ARM* Architecture V5TE), is designed forhigh-performance and low-power; leading the industry in mW/MIPs. The Intel ® XScale microarchitecture integrates a bus controller and an interrupt controller around a core processor, withAPIs and Testbench White Paper 15