Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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Intel ® GW80314 I/O Processor DMA and XOR LibraryGeneral Notes8.0 General Notes8.1 Cache Implications Using Append Resume MacrosFor a DMA or XOR descriptor, when the data cache policy requires a cache clean below are thenumber of cachelines required to be cleaned:• DMA 2 cache lines• XOR 4 source 2 cache lines• XOR 8 source 3 cache lines• XOR 16 source 5 cache lines8.2 GCSR is used to set Descriptor Completion InterruptsThe gscr is the Channel General Control and Status Register and is used to set interrupt completioninterrupts. Note this is a channel global register verses a descriptor specific flag. So the channelchain state must be determined when doing appends and using interrupts to identify end of chain.8.3 Using ResumeWhen the GCSR OP_CMD remains the same for a channel, the following sequence can be used toappend and execute the next descriptor without regard to the state of execution for the existingchain (whether the existing chain is currently executing or complete).......Append goes here.*GCSR_REGISTER |=(RESUME|GO);......8.4 Changing from DMA to XOR Descriptors on the SameChannelWhen changing the the GCSR OP_CMD, the channel should be INACTIVE and the existingchained descriptors should be complete. This is required since the GCSR is used to specify theoperation command (OP_CMD).8.5 Error HandlingIf a descriptor generates an error condition, the DMA/XOR engine will stop during the executionof that descriptor.28 APIs and Testbench White Paper
Intel ® GW80314 I/O Processor DMA and XOR LibraryGeneral NotesBy setting the interrupt enable for error conditions, the interrupt handler can record the stateinformation of the DMA/XOR engine registers. The register information includes the address ofthe subsequent descriptor to the descriptor causing the error condition (Channel Next DescriptorAddress Register). Determine the descriptor address of the descriptor causing the interrupt andinvoke the application error handling routine.8.6 DMA/XOR Channel Arbitration for the SFN PortThe four channels use round robin to arbitrate for the port. The port can execute a read and write todifferent destinations ports concurrently. Each Channel can have 2 reads and 2 writes outstanding.Each read or write can be up to the size of the 256 byte buffers.8.7 GNUPro Toolset Compiler OptimizationThe GNUPro toolset offers compiler setting of -O0 through -O3. Each level has its uniquecharacteristic in terms of level of optimization and object size. Level -O2 was found to provide thebest performance for descriptor processing. Level -O0 is the default.8.8 Reclamation of DescriptorsThere are alternate methods to select the time when to do reclamation of executed descriptors.These include:• Wait until a request for a free descriptor returns a null pointer indicating there are no freedescriptors remaining in that channel.• Wait till slack time in processing and call lib_reclaim().• Set timer and call in intervals.8.9 Extending Library to Run with Multiple ThreadsThe Library is single threaded. However, all functions take a pointer to the data structureXORDma_GW80314_Type. This feature simplifies porting to multiple threads applications. Theissue becomes mapping the DMA and XOR controllers to multiple threads.8.10 When Using Append / Resume SequenceAPPEND(LAST,NEXT,PORT)• LAST should be the uncached/unbuffered address of the last descriptor for that channel.Thiseliminates a cache clean.• NEXT should be the physical address of the descriptor appended.• PORT is the port where the descriptor resides (sdram = 4, sram = 3)• The append followed by the resume operation should only be separated by ”,” operator toeliminate possibility of instruction reordering by compiler.APIs and Testbench White Paper 29
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