Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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Intel ® GW80314 I/O Processor DMA and XOR LibraryTest Bench Library Function PrototypesAppendix G Test Bench Library Function PrototypesG.1 bench.cG.1.1int main(void);ItemDescriptionPrototype int main(void);Input NoneOutput NonePurposeOperationG.1.2 void print_title(enum build b)Testbench initialization and control of test cases run based on keyboard input from menuselectionInitialization• Allocates descriptor manager data structure• Allocated memory for descriptor processing and data and records to global structure• Chains in interrupt handlers• Enables and routes irq and fiq interruptsMenu Selection• Infinite while loop that call test cases based on keyboard input from MenuItemDescriptionPrototype void print_title(enum build b)Input enum build identifies the test case.Output NonePurpose To print the test case title to stdio and file bnech.outOperation Based on input parameter C switch statement selects corresponding printf statements.G.1.3void generate_src_dst(void);ItemDescriptionPrototype void generate_src_dst(void);Input NoneOutput NonePurpose Reset state of memory before each test case is run.OperationResets state of descriptor and data memory regions to 0. Then writes test data to sourcelocations.80 APIs and Testbench White Paper
Intel ® GW80314 I/O Processor DMA and XOR LibraryTest Bench Library Function PrototypesG.2 lib_demo_cases.cG.2.1void lib_demo_sdram(void)void lib_demo_sram(void)ItemPrototypeInputOutputPurposeOperationvoidvoidNoneNonelib_demo_sdram(void)lib_demo_sram(void)DescriptionTo demonstrate functionality of DMA/XOR Library including error detection using interrupthandler. sdram sets up descriptors from sdram while sram sets up descriptors in sram.Demonstrated functionality includes (this is commented and handled by main():• Allocate memory for descriptor manager• malloc the memory map• chain in the interrupt handler• set global coalescingCalled by case:• initialize the DMA/XOR Library data structure inside descriptor manager (setup descriptorFree Stack and Post Queues, initialize DMA/XOR engines for appends)• set descriptor processing memory range as 001• stat data memory range as 000• execute DMA descriptor transactions• use append and reclaiming descriptors• reclaim reports any DMA transfer error since an error causes a interrupt to occur and theinterrupt handler records the csr value to the frame. For an error the csr non-zeros. Thenon-zero csr value is identified by reclaim.APIs and Testbench White Paper 81
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ContentsE.2.10 void * lib_q_get(Xor
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Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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