Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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Intel ® GW80314 I/O Processor DMA and XOR LibraryData Cache Policy Mechanics4.0 Data Cache Policy Mechanics4.1 IntroductionData cache policies can be customized for each memory page allowing different software operationsto interface with a tailored Data Cache Policy. Data Cache policies are setup and controlled using theIntel ® XScale Microarchitecture page tables. Also see ARM Architecture Reference Manual for adescription of the Page Table Translation process.4.2 Page TablesThe Intel ® XScale microarchitecture extends the page attributes defined by the C and B bits inthe page descriptors with an additional X bit. This bit allows four more attributes to be encodedwhen X=1. These new encodings include allocating data for the mini-data cache and write-allocatecaching. A full description of the encodings can be found in the Intel ® XScale MicroarchitectureProgrammer’s Reference Manual.The Intel ® XScale microarchitecture retains ARM definitions of the C and B encoding when X =0, which is different than the first generation Intel ® StrongARM products. The memory attributefor the mini-data cache has been moved and replaced with the write-through caching attribute.When write-allocate is enabled, a store operation that misses the data cache (cacheable data only)generates a line fill. When disabled, a line fill only occurs when a load operation misses the datacache (cacheable data only).Write-through caching causes all store operations to be written to memory, whether they arecacheable or not cacheable. This feature is useful for maintaining data cache coherency.These attributes are programmed in the translation table descriptors, which are highlighted inTable 1, “First-level Descriptors” on page 19, Table 2, “Second-level Descriptors for Coarse PageTable” on page 19 and Table 3, “Second-level Descriptors for Fine Page Table” on page 19. Twosecond-level descriptor formats have been defined for Intel ® XScale microarchitecture, one isused for the coarse page table and the other is used for the fine page table.Note:P bit is not implemented.18 APIs and Testbench White Paper
Intel ® GW80314 I/O Processor DMA and XOR LibraryData Cache Policy MechanicsTable 1.First-level Descriptors31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0SBZ 0 0Coarse page table base address P Domain SBZ 0 1Section base address SBZ TEX AP P Domain 0 C B 1 0Fine page table base address SBZ P Domain SBZ 1 1Table 2.Second-level Descriptors for Coarse Page Table31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0SBZ 0 0Large page base address TEX AP3 AP2 AP1 AP0 C B 0 1Small page base address AP3 AP2 AP1 AP0 C B 1 0Extended small page base address SBZ TEX AP C B 1 1Table 3.Second-level Descriptors for Fine Page Table31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0SBZ 0 0Large page base address TEX AP3 AP2 AP1 AP0 C B 0 1Small page base address AP3 AP2 AP1 AP0 C B 1 0Tiny Page Base Address TEX AP C B 1 1The P bit controls ECC.Note:P bit is not implemented.The TEX (Type Extension) field is present in several of the descriptor types. In the Intel ® XScale microarchitecture, only the LSB of this field is used; this is called the X bit.A Small Page descriptor does not have a TEX field. For these descriptors, TEX is implicitly zero;that is, they operate as when the X bit had a ‘0’ value. The X bit, when set, modifies the meaning ofthe C and B bits.APIs and Testbench White Paper 19
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