Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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Intel ® GW80314 I/O Processor DMA and XOR LibraryGeneral Notes• Remember if LAST is not mapped to uncached memory address, then Flush 2 cachelines.8.11 Append Operation SequencingWhen doing append, the Channel Next Descriptor Address Register should be the Last Descriptorfield updated since it contains the LAST bit. Therefore, the chain can be in any state of executionbut will not attempt to continue to the next descriptor while the append is incomplete. See macrosequence.#define APPEND(L,N,P)( ((Header_Type*)(L))->nd_tcr=ND_TCR_APPND_VAL(N,P),(((Header_Type *)(L))->nd_addr_m=0x0),(((Header_Type *)(L))->nd_addr_l=((unsigned long)N)))8.12 DMA or XOR Descriptors Variables should be VolatileBy making variables volatile, this eliminates the potential for compiler optimization altering thevariable. An example would be the global variables used for append:volatile void * chainHeadXORDMA[4];//Global variable used for appendvolatile void * chainTailXORDMA[4];//Global variable used for appendvolatile XorDma_80314_Type *desc_mgr;30 APIs and Testbench White Paper
Intel ® GW80314 I/O Processor DMA and XOR LibraryConclusion9.0 ConclusionThe purpose of the GW80314 DMA/XOR Library is to provide a fast ramp for developers byproviding a turnkey optimized solution that synergistically combines with exiting Intel collateral(See Appendix J, “Related Documents” for related web documents).APIs and Testbench White Paper 31
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