Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

Intel ® GW80314 I/O Processor DMA and XOR LibraryGeneral Notes8.0 General Notes8.1 Cache Implications Using Append Resume MacrosFor a DMA or XOR descriptor, when the data cache policy requires a cache clean below are thenumber of cachelines required to be cleaned:• DMA 2 cache lines• XOR 4 source 2 cache lines• XOR 8 source 3 cache lines• XOR 16 source 5 cache lines8.2 GCSR is used to set Descriptor Completion InterruptsThe gscr is the Channel General Control and Status Register and is used to set interrupt completioninterrupts. Note this is a channel global register verses a descriptor specific flag. So the channelchain state must be determined when doing appends and using interrupts to identify end of chain.8.3 Using ResumeWhen the GCSR OP_CMD remains the same for a channel, the following sequence can be used toappend and execute the next descriptor without regard to the state of execution for the existingchain (whether the existing chain is currently executing or complete).......Append goes here.*GCSR_REGISTER |=(RESUME|GO);......8.4 Changing from DMA to XOR Descriptors on the SameChannelWhen changing the the GCSR OP_CMD, the channel should be INACTIVE and the existingchained descriptors should be complete. This is required since the GCSR is used to specify theoperation command (OP_CMD).8.5 Error HandlingIf a descriptor generates an error condition, the DMA/XOR engine will stop during the executionof that descriptor.28 APIs and Testbench White Paper