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Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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<strong>Intel</strong> ® GW80314 I/O <strong>Processor</strong> <strong>DMA</strong> <strong>and</strong> <strong>XOR</strong> <strong>Library</strong>Test Bench <strong>Library</strong> Function PrototypesAppendix G Test Bench <strong>Library</strong> Function PrototypesG.1 bench.cG.1.1int main(void);ItemDescriptionPrototype int main(void);Input NoneOutput NonePurposeOperationG.1.2 void print_title(enum build b)Testbench initialization <strong>and</strong> control of test cases run based on keyboard input from menuselectionInitialization• Allocates descriptor manager data structure• Allocated memory for descriptor processing <strong>and</strong> data <strong>and</strong> records to global structure• Chains in interrupt h<strong>and</strong>lers• Enables <strong>and</strong> routes irq <strong>and</strong> fiq interruptsMenu Selection• Infinite while loop that call test cases based on keyboard input from MenuItemDescriptionPrototype void print_title(enum build b)Input enum build identifies the test case.Output NonePurpose To print the test case title to stdio <strong>and</strong> file bnech.outOperation Based on input parameter C switch statement selects corresponding printf statements.G.1.3void generate_src_dst(void);ItemDescriptionPrototype void generate_src_dst(void);Input NoneOutput NonePurpose Reset state of memory before each test case is run.OperationResets state of descriptor <strong>and</strong> data memory regions to 0. Then writes test data to sourcelocations.80 <strong>APIs</strong> <strong>and</strong> Testbench White Paper

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