Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
<strong>Intel</strong> ® GW80314 I/O <strong>Processor</strong> <strong>DMA</strong> <strong>and</strong> <strong>XOR</strong> <strong>Library</strong><strong>DMA</strong><strong>XOR</strong>80314.h#define CH0_ND_TCR (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x020)#define CH0_GCSR (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x024)#define CH0_CRC_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x028)#define CH0_CRC_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x02c)#define CH0_CRC (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x030)#define CH0_SRC01_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x040)#define CH0_SRC01_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x044)#define CH0_SRC02_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x048)#define CH0_SRC02_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x04c)#define CH0_SRC03_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x050)#define CH0_SRC03_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x054)#define CH0_SRC04_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x058)#define CH0_SRC04_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x05c)#define CH0_SRC05_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x060)#define CH0_SRC05_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x064)#define CH0_SRC06_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x068)#define CH0_SRC06_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x06c)#define CH0_SRC07_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x070)#define CH0_SRC07_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x074)#define CH0_SRC08_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x078)#define CH0_SRC08_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x07c)#define CH0_SRC09_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x080)#define CH0_SRC09_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x084)#define CH0_SRC10_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x088)46 <strong>APIs</strong> <strong>and</strong> Testbench White Paper