Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

Intel ® GW80314 I/O Processor DMA and XOR LibraryIntel ® GW80314 I/O Processor Component Overview• identifying code as cacheable or non-cacheable.• selecting between the mini-data cache or data cache.• write-back or write-through data caching.• enabling data write allocation policy.• enabling the write buffer to coalesce stores to external memory.See the Intel ® XScale Microarchitecture Programmer’s Reference Manual for more detail.3.3.3 Interrupt ControllerAn interrupt controller is implemented on the Intel ® XScale microarchitecture that providesmasking of interrupts and the ability to steer interrupts to FIQ or IRQ. It is accessed throughCoprocessor 13 registers. See the Intel ® XScale Microarchitecture Programmer’s ReferenceManual for more detail.3.3.4 Data CacheThe Intel ® XScale microarchitecture implements a 32-Kbyte, a 32-way set associative data cacheand a 2-Kbyte, 2-way set associative mini-data cache. Each cache has a line size of 32 bytes,supports write-through or write-back caching.The data/mini-data cache is controlled by page attributes defined in the MMU Architecture and bycoprocessor 15.See the Intel ® XScale Microarchitecture Programmer’s Reference Manual discusses all this inmore detail.APIs and Testbench White Paper 17