Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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Intel ® GW80314 I/O Processor DMA and XOR LibraryDMAXOR80314.h#define GCSR_STOP_EN (1
Intel ® GW80314 I/O Processor DMA and XOR LibraryDMAXOR80314.h* }GCSR_OP_CMD;* GCSR = set any other bits in GCSR. For example setting interrupts.* L = Last descriptor* N = Next descriptor* P = Port location for appended desc* typedef enum {* HLP = 0,* PCI_1= 1,* PCI_2= 2,* CIU_SRAM=3,* SDRAM= 4,* DMAXOR= 5,* GIGE= 6,* DIRECT= 7* }PORT;* ADDR = Address of descriptor* ND_ADDR_L= Next descriptor address Least significant bits* ND_ADDR_M= Next descriptor address Most significant bits*******************************************************************************///When using uncached memory region for decriptor processing, N must be SDRAM_UCUBmapping#define APPEND_RESUME(CH,CMD,GCSR,L,N,P)(APPEND(L,N,P),SET_GCSR_RESUME(CH,CMD,GCSR))#define APPEND_RESUME_SVLAST(CH,CMD,GCSR,L,N,P)(APPEND_RESUME(CH,CMD,GCSR,L,N,P),LOAD_CHAIN_TAIL(P,CH,N))//Afer APPEND but before Set GCSR, remember to call _Clean_D_Cache_Line for L(prior decriptor)#define APPEND(L,N,P) ( ((Header_Type*)(L))->nd_tcr=ND_TCR_APPND_VAL(N,P),(((Header_Type*)(L))->nd_addr_m=0x0),(((Header_Type *)(L))->nd_addr_l=((unsigned long)N)))#define SET_GCSR_RESUME(CH,CMD,GCSR) (*CH_GCSR(CH)=(unsigned int)((unsignedint)GCSR_RESUME|(unsigned int)CMD|(unsigned int)GCSR|(unsignedint)(GCSR_GO|GCSR_CHAIN)))//Utilites#define SET_DESC_LAST_LL(ADDR)(((Header_Type *)(ADDR))->nd_addr_l |= CNDAR_LAST)#define LOAD_CHAINTAIL(CH,N)(chainTailDMAXOR[CH] = (void *)N)APIs and Testbench White Paper 59
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Intel ® GW80314 I/O ProcessorDMA a
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ContentsContents1.0 Introduction...
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ContentsE.2.10 void * lib_q_get(Xor
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Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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