Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

Intel ® GW80314 I/O Processor DMA and XOR LibraryIntroduction1.0 IntroductionIntel provides customers of the Intel ® GW80314 I/O processor 1 (GW80314) an optimized turnkeyLibrary solution for DMA/XOR applications to provide a fast development ramp. The DMA/XORLibrary synergistically combines with existing Intel collateral (See Section J, “RelatedDocuments” on page 90 for related web documents).The turnkey Optimized XOR and DMA Library consists of:— DMA/XOR register set .h files.— Functions to set Data Cache Policy for specified memory pages.— Integrated Descriptor Handling.— Required macros.— Interrupt handler with setup of Interrupt Controller.— Rules for optimization.— Test bench demonstrating Library implementation.1.1 Demonstrate Libraries Testbench MenuThe Library menu is shown below. The testbench provides menu driven test cases implementing theLibraries.Note:DMA/XOR descriptors can be run from SRAM or SDRAM.1. SDRAM: DMA with crc and XOR Library (Random Channel and DMA vs.XOR)2. SRAM : DMA with crc and XOR Library (Random Channel and DMA vs.XOR)• Option 2 is not currently available.1.1.1 Description of Demonstration CasesThe DMA/XOR engine has four identical channels operating independently. They arbitrate usinground robin for the port interfacing the switch fabic network (see Figure 1). Each channel mayfunction as a DMA or XOR engine.The Library Demo cases iterate 30000 times. For each iteration, a random selection is madebetween each of the four channels and whether to perform a DMA or XOR transaction on thatchannel. An aligned buffer is requisitioned from the Free Stack as a DMA or XOR descriptor and iscompleted and flushed from the Data Cache to SDRAM or SRAM. If it is a DMA transaction, thena CRC32 calculation is initiated as well.Following the transaction being completed, the DMA/CRC32 or XOR transaction results arevalidated for accuracy and completeness.1. ARM* architecture compliant.APIs and Testbench White Paper 9