Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
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<strong>Intel</strong> ® GW80314 I/O <strong>Processor</strong> <strong>DMA</strong> <strong>and</strong> <strong>XOR</strong> <strong>Library</strong><strong>DMA</strong><strong>XOR</strong>80314.h#define CH3_SRC05_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x064)#define CH3_SRC06_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x068)#define CH3_SRC06_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x06c)#define CH3_SRC07_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x070)#define CH3_SRC07_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x074)#define CH3_SRC08_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x078)#define CH3_SRC08_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x07c)#define CH3_SRC09_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x080)#define CH3_SRC09_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x084)#define CH3_SRC10_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x088)#define CH3_SRC10_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x08c)#define CH3_SRC11_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x090)#define CH3_SRC11_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x094)#define CH3_SRC12_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x098)#define CH3_SRC12_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x09c)#define CH3_SRC13_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x0a0)#define CH3_SRC13_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x0a4)#define CH3_SRC14_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x0a8)#define CH3_SRC14_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x0ac)#define CH3_SRC15_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x0b0)#define CH3_SRC15_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH3_OFFSET +0x0b4)//CH == Channel 0 - 352 <strong>APIs</strong> <strong>and</strong> Testbench White Paper
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