Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
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<strong>Intel</strong> ® GW80314 I/O <strong>Processor</strong> <strong>DMA</strong> <strong>and</strong> <strong>XOR</strong> <strong>Library</strong><strong>DMA</strong><strong>XOR</strong>80314.h#define CH1_SRC01_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x044)#define CH1_SRC02_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x048)#define CH1_SRC02_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x04c)#define CH1_SRC03_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x050)#define CH1_SRC03_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x054)#define CH1_SRC04_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x058)#define CH1_SRC04_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x05c)#define CH1_SRC05_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x060)#define CH1_SRC05_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x064)#define CH1_SRC06_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x068)#define CH1_SRC06_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x06c)#define CH1_SRC07_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x070)#define CH1_SRC07_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x074)#define CH1_SRC08_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x078)#define CH1_SRC08_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x07c)#define CH1_SRC09_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x080)#define CH1_SRC09_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x084)#define CH1_SRC10_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x088)#define CH1_SRC10_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x08c)#define CH1_SRC11_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x090)#define CH1_SRC11_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x094)#define CH1_SRC12_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x098)#define CH1_SRC12_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +48 <strong>APIs</strong> <strong>and</strong> Testbench White Paper
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