12.07.2015 Views

Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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<strong>Intel</strong> ® GW80314 I/O <strong>Processor</strong> <strong>DMA</strong> <strong>and</strong> <strong>XOR</strong> <strong>Library</strong><strong>Library</strong> Function PrototypesE.2.8 inline int lib_postq_appnd_resume_sdram(XorDma_80314_Type *mgr, void * frame,enum PORT port,enum GCSR_OP_CMDcmd,unsigned int gcsr,enum CHANNEL channel)ItemPrototypeInputDescriptioninline int lib_postq_appnd_resume_sdram(XorDma_80314_Type * mgr, void *frame,enum PORT port,enum GCSR_OP_CMD cmd,unsigned int gcsr,enum CHANNELchannel)XorDma_80314_Type * mgr: Pointer to XorDma_80314_Type being usedvoid * frame: The frame to be appendedenum PORT port:typedef enum {HLP = 0,PCI_1=1,PCI_2=2,CIU_SRAM=3,SDRAM=4,<strong>DMA</strong><strong>XOR</strong>=5,GIGE=6,DIRECT=7}PORTenum GCSR_OP_CMD cmd:enum{<strong>DMA</strong>_CMD,<strong>XOR</strong>_CMD}GCSR_OP_CMDunsigned int gcsr: value to be loaded to gcsr register to initiate append.enum CHANNEL channel:channel: either Channel 0, 1, 2, or 3OutputPurposeOperationSUCCESS == 0FAIL == non-zeroTo post frame to post queue, append frame to a channel specific chain of <strong>DMA</strong> descriptors<strong>and</strong> set channel resume to initiate transfer.NOTE: When using cached memory, flush descriptor to RAM before calling function.• Post to queue• Append to Channel Chain• Reset chain chainTail<strong>XOR</strong><strong>DMA</strong>[]pointer• Set channel resumeE.2.9int lib_reclaim(XorDma_80314_Type * mgr,enum CHANNEL channel)ItemDescriptionPrototype int lib_reclaim(XorDma_80314_Type * mgr, enum CHANNEL channel)Inputmgr: XorDma_80314_Type data structure usingchannel: either Channel 0, 1, 2, or 374 <strong>APIs</strong> <strong>and</strong> Testbench White Paper

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