Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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Intel ® GW80314 I/O Processor DMA and XOR LibraryIntel ® GW80314 I/O Processor Component OverviewFigure 2.DMA/XOR EngineDMA_ARB(Arbitrate for Access to SFN Gasket)SelectDMA_CHAN0DMA_CHAN1 DMA_CHAN2 DMA_CHAN3Data InDMA_MUXHeader Info(Mux Channel Data and Header Info to SFN Gasket)CRC/XOR DataDMA_SFN_GSKTSFN OutSFN InB1970-013.2.2 DMA/XOR FeaturesThis block has the following features:• Round robin arbitration between the four channel for the SFN port• Four channel support; each channel operates independently• Data transfer from and to any port and memory fill as a DMA engine• XOR operation, and parity checking as an XOR engine• Scatter gather (or Linked-List) and direct modes• XOR operation of up to 16 blocks of data• Directly fill the store queue with the first block of XOR data (optional)• Interrupt on completed segment, chain, and error (all optional)14 APIs and Testbench White Paper
Intel ® GW80314 I/O Processor DMA and XOR LibraryIntel ® GW80314 I/O Processor Component Overview• Mode selectable byte/word conversion on transferred data• Ability to launch DMA or XOR operation from a single write transaction• Calculate CRC on the DMA transferred data based on the CRC-32C algorithm required by theiSCSI Specification• Pipelines read requests or read and write requests for better performance• Go/stop/halt control of data transfer operationFigure 3.DMA/XOR ChannelAHB RegistersDirect_FillXOR Store QueueXOR ControlRegister UpdateControls64-Bit Data Path256 Byte Accumulator32-Bit CRCFSMCRC GeneratorCRCControlPacketData Out64-Bit Data Path32-Bit CRCSFN Packet InPacketHeaderInfo OutB1971-013.2.3 Memory: SRAM and SDRAMFor DMA/XOR Descriptor processing both SRAM and SDRAM can be used. Both are mapped tocache and both can be set of any of the XScale Data Cache Policies.3.3 Intel ® XScale Microarchitecture3.3.1 OverviewThe Intel ® XScale microarchitecture (compliant with ARM* Architecture V5TE), is designed forhigh-performance and low-power; leading the industry in mW/MIPs. The Intel ® XScale microarchitecture integrates a bus controller and an interrupt controller around a core processor, withAPIs and Testbench White Paper 15
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Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

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