Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
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<strong>Intel</strong> ® GW80314 I/O <strong>Processor</strong> <strong>DMA</strong> <strong>and</strong> <strong>XOR</strong> <strong>Library</strong><strong>DMA</strong><strong>XOR</strong>80314.h#define CH0_SRC10_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x08c)#define CH0_SRC11_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x090)#define CH0_SRC11_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x094)#define CH0_SRC12_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x098)#define CH0_SRC12_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x09c)#define CH0_SRC13_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x0a0)#define CH0_SRC13_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x0a4)#define CH0_SRC14_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x0a8)#define CH0_SRC14_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x0ac)#define CH0_SRC15_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x0b0)#define CH0_SRC15_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x0b4)//Channel 1#define CH1_SRC_ADDR_M (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x000)#define CH1_SRC_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x004)#define CH1_DST_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x008)#define CH1_DST_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x00c)#define CH1_TCR1 (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x010)#define CH1_TCR2 (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x014)#define CH1_ND_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x018)#define CH1_ND_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x01c)#define CH1_ND_TCR (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x020)#define CH1_GCSR (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x024)#define CH1_CRC_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x028)#define CH1_CRC_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x02c)#define CH1_CRC (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET + 0x030)#define CH1_SRC01_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH1_OFFSET +0x040)<strong>APIs</strong> <strong>and</strong> Testbench White Paper 47
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