Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...

Intel ® GW80314 I/O Processor DMA and XOR LibraryDMAXOR80314.h#define LOAD_CHAIN_TAIL(P,CH,N)(chainTailDMAXOR[CH] = (void *)UCUB(P,N))#define CLEAR_GCSR_STATUS(CH) (*CH_GCSR(CH)=GCSR_STATUS_BITS)//Init Linked List with first descriptor//CH = Channel, M = Most signifcant address, L = Least sig address, NT = nd_tcr#define LOAD_HEAD_CLR_GCSR(CH,M,L,NT)(LOAD_ND_ADDR_REG(CH,L,M),LOAD_ND_TCR_REG(CH,NT),SET_TCR2_REG_BC_0(CH),CLEAR_GCSR_STATUS(CH))#define SET_INTERRUPT(CH)(*CH_GCSR(CH)|=(unsigned long)(GCSR_DONE_EN))#define SET_GCSR_CHAIN_GO(CH,CMD,GCSR)(*CH_GCSR(CH)|=(unsignedlong)(GCSR_CHAIN|GCSR_GO|CMD|GCSR))#define LOAD_ND_ADDR_REG(CH,ND_ADDR_L,ND_ADDR_M) ((*CH_ND_ADDR_L(CH)=(unsignedlong)(ND_ADDR_L)),(*CH_ND_ADDR_M(CH)=(unsigned long)(ND_ADDR_M)))#define LOAD_ND_TCR_REG(CH,VAL ) (*CH_ND_TCR(CH)= (unsigned long)(VAL ))#define SET_TCR2_REG_BC_0(CH) (*CH_TCR2(CH)&= 0xf8000000)//Check Channel Status#define GET_CH_STATUS(CH)(*CH_GCSR(CH) & GCSR_DACT)#define GET_GCSR(CH)(*CH_GCSR(CH))//Dont use this. Rolled up to larger APPEND macro.#define ND_TCR_APPND_VAL(N,P)( (CNDCR_ND_PORT(P))|CNDCR_ND_BLOCKS( ( (( Header_Type*)(N))->tcr1 ) & 0xf )) // blocks from next//Alignment//DMA Descriptors align 64 byte boundries. 2 cache lines.#define DMA_ALIGN(VAL)((((unsigned long)VAL) & 0x3f)?((((unsigned long)VAL))+(64 -(((unsigned long)VAL) & 0x3f))):((unsigned long)VAL))//XOR Descriptors align 256 bytes. 5 cache lines.#define XOR_ALIGN(VAL)((((unsigned long)VAL) & 0xff)?((((unsigned long)VAL))+(256 -(((unsigned long)VAL) & 0xff))):((unsigned long)VAL))//Redboot memory map#define SDRAM_CB(addr) /*Policy 111*/( ((unsigned long)(addr)) & ~0xe0000000)#define SDRAM_UCUB(addr) /*Policy 000*/((((unsigned long)(addr)) & ~0xe0000000) |SDRAM_000_BASE() )#define SDRAM_PHY(addr) ((((unsigned long)(addr)) & ~0xe0000000) |60 APIs and Testbench White Paper