Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
Intel(R) IQ80315 I/O Processor DMA and XOR Library APIs and ...
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<strong>Intel</strong> ® GW80314 I/O <strong>Processor</strong> <strong>DMA</strong> <strong>and</strong> <strong>XOR</strong> <strong>Library</strong><strong>DMA</strong><strong>XOR</strong>80314.h* Redboot Defined************************************************************/#define BASE_CREGS#define RAM_LOWER#define RAM_UPPER0x501000000x000000000x10000000/************************************************************* 80314 <strong>DMA</strong>/<strong>XOR</strong> Block************************************************************/#define <strong>DMA</strong><strong>XOR</strong>_BASE (BASE_CREGS + 0x5000)#define CH0_OFFSET#define CH1_OFFSET#define CH2_OFFSET#define CH3_OFFSET0x0000x1000x2000x300enum CHANNEL{CH0 = 0,CH1 = 1,CH2 = 2,CH3 = 3};#define NUM_CHANNELS0x4//Channel 0#define CH0_SRC_ADDR_M (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x000)#define CH0_SRC_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET +0x004)#define CH0_DST_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x008)#define CH0_DST_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x00c)#define CH0_TCR1 (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x010)#define CH0_TCR2 (volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x014)#define CH0_ND_ADDR_M(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x018)#define CH0_ND_ADDR_L(volatile unsigned long *)(<strong>DMA</strong><strong>XOR</strong>_BASE + CH0_OFFSET + 0x01c)<strong>APIs</strong> <strong>and</strong> Testbench White Paper 45
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