D2.1 Requirements and Specification - CORBYS

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D2.1 Requirements and Specification o Operating systems required/supported: MS Windows XP/Vista/7 7.4.2 Assumptions and Dependencies Internal � PSI depend on SAWBB � DSI depend on SAWBB � OSI depend on SAWBB � All other modules depend on SAWBB 7.5 Robot response to a situation (Task 4.3, UR) For an effective control system, the behaviour is divided into reflexive and learned (reflective) behaviour. A hardware and software co-design will be used for this purpose. Reflexes, as in humans, are pre-compiled, i.e. they are automatic without the need for elaboration or thinking. In CORBYS, this will be realised via hardware implemented algorithms for obstacle avoidance, navigation, safety issues etc. Learned reflective behaviour on the other hand is constantly updated and adapted to the situation, this will be implemented in software. Hardware Reflex Capability will entail the implementation of invariant reflexes of the system such as avoidance of certain obstacles, using low level recognition algorithms realised in an FPGA to allow for fast prototyping and re-configurability. On the other hand, Software Learning Modules will realise the learning behaviour in software using machine learning for pattern discovery, pattern-directed inference and learning and refinement of the cognitive map. 7.5.1 Functional Requirements 7.5.1.1 Processes Inputs Requirement No. RRS1 Name: Inputs and connections to the FPGA sub-system from the mechatronics sub-system Description: Any inputs directly feeding into the FPGA sub-system, signal conditioning, Analog to Digital conversion (ADC), data rate, data bus width, data format etc. Number and type of the sensors attached to the subject Reason / Comments: Indicative priority Mandatory Requirement No. RRS2 Name: Inputs to FPGA sub-system from various software modules Description: Such as the Situational Awareness modules etc. Reason / Comments: Indicative priority Mandatory Requirement No. RRS3 Name: Scalability to support inputs and connections from hardware transducers/devices Description: Within the scope and duration of the project, the FPGA sub-system should have enough I/O capability available for any future hardware transducers, their data rate, data bus width, data 68
D2.1 Requirements and Specification format, signal conditioning, Analog to Digital conversion etc. Reason / Comments: Indicative priority Desirable Requirement No. RRS4 Name: Continuous monitoring Description: Any physical quantities or situations, that may have an impact on the power requirements and the architecture of the FPGA hardware sub-system, need to be monitored or may need to be polled continuously for any purpose and their criticality. Also special requirements such as signal conditioning, ADC need to be identified. Reason / Comments: Indicative priority Mandatory Requirement No. RRS5 Name: Event handling Description: Events that need to be taken care of during the normal execution and their criticality. Events that may have an impact on the power requirements and architecture of the FPGA hardware sub-system such as priority interrupts etc Reason / Comments: Indicative priority Mandatory Processing Requirement No.: RRS6 Name: Identification of reflexive capability to be enabled by the FPGA sub-system. Description: To identify the feasibility in terms of implementation in the FPGA Hardware. Reason / Comments: Indicative priority Mandatory Requirement No.: RRS7 Name: Identification of ‘Navigation’ related reflexive behaviour enabled by the FPGA sub-system. Description: To identify the feasibility in terms of implementation in the FPGA Hardware. Reason / Comments: Indicative priority Mandatory Requirement No.: RRS8 Name: Identification of ‘Obstacle avoidance’ related reflexive behaviour enabled by the FPGA subsystem. Description: To identify the feasibility in terms of implementation in the FPGA Hardware. Reason / Comments: Indicative priority Mandatory Requirement No.: RRS9 Name: Identification of ‘Safety’ related reflexive behaviour enabled by the FPGA sub-system. Description: To identify the feasibility in terms of implementation in the FPGA Hardware. Reason / Comments: Indicative priority Mandatory Requirement No.: RRS10 Name: Identification of open and closed loop processes for the FPGA sub-system Description: Reason / Comments: Reason: For example, in a closed loop process, it may be required to implement a closed loop controller algorithm in an on board processor or in FPGA, so it is important to know beforehand. 69
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CORBYS Cognitive Control Framework
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D2.1 Requirements and Specification
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D2.1 Requirements and Specification - CORBYS

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