D2.1 Requirements and Specification - CORBYS

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D2.1 Requirements and Specification Indicative priority Mandatory Requirement No.: RRS11 Name: Selection of off-the-shelf FPGA device Description: This depends on the above factors and the overall functional requirement from the FPGA sub-system Reason / Comments: Indicative priority Mandatory Requirement No.: RRS12 Name: Selection/design of custom or off-the-shelf FPGA board for the selected FPGA device Description: This depends on the above factors and the overall functional requirement from the FPGA sub-system Reason / Comments: Indicative priority Mandatory Requirement No.: RRS13 Name: Additional processing and memory devices for the FPGA board Description: This depends on the above factors and the overall functional requirement from the FPGA sub-system Reason / Comments: Indicative priority Mandatory Requirement No.: RRS14 Name: List of states, conditions and transitions Description: This is derived from the functionality of the FPGA sub-system Reason / Comments: Indicative priority Mandatory Requirement No.: RRS15 Name: Reconfiguration and reprogrammable FPGA sub-system Description: The implemented hardware sub-system and the FPGA board should be reprogrammable, reconfigurable and have enough processing capability to support any future requirements within the scope and duration of the project Reason / Comments: Indicative priority Desirable Requirement No.: RRS16 Name: Sensor input level 0 processing on the FPGA sub-system Description: If FPGA sub-system is situated between mechatronics and software/cognitive sub-systems, raw sensor data can be pre-processed in real-time before it is presented to the software modules of CORBYS. To be discussed with partners during specification stage Reason / Comments: Reason: Fast real-time processing sensor input Indicative priority Optional Output Requirement No. RRS17 Name: Outputs and connections to the FPGA sub-system from the mechatronics sub-system Description: Any outputs directly feeding into the mechatronics sub-system, signal conditioning, Analog to Digital conversion (ADC), data rate, data bus width, data format etc. Number and type of the sensors attached to the subject Reason / Comments: Indicative priority Mandatory 70
D2.1 Requirements and Specification Requirement No. RRS18 Name: Outputs to FPGA sub-system from various software modules Description: Such as the Situational Awareness modules etc. Reason / Comments: Indicative priority Mandatory Requirement No. RRS19 Name: Scalability to support outputs and connections from hardware transducers/devices Description: Within the scope and duration of the project, the FPGA sub-system should have enough I/O capability available for any future hardware transducers, their data rate, data bus width, data format, signal conditioning, Analog to Digital conversion etc. Reason / Comments: Indicative priority Desirable Requirement No. RRS20 Name: Continuous stimulation Description: Any physical quantities or situations, that may have an impact on the power requirements and the architecture of the FPGA hardware sub-system, need to be stimulated continuously for any purpose and their criticality. Also special requirements such as signal conditioning, ADC need to be identified. Reason / Comments: Indicative priority Mandatory Requirement No. RRS21 Name: Event handling Description: Events that need to be taken care of during the normal execution and their criticality. Events that may have an impact on the power requirements and architecture of the FPGA hardware sub-system such as priority interrupts etc Reason / Comments: Indicative priority Mandatory Dataflow Requirement No.: RRS22 Name: Data paths to/from FPGA sub-system Description: Identify any other data paths that may be required to be implemented in the FPGA subsystem. Reason / Comments: Indicative priority Optional Requirement No.: RRS23 Name: Any data paths required VIA FPGA sub-system Description: This is when FPGA sub-system is also working as a middle-man between the software and mechatronics sub-system. Reason / Comments: Indicative priority Optional 7.5.1.2 Interfaces User interfaces, hardware/software interfaces i.e. what the system must connect to. Requirement No.: RRS24 Name: FPGA sub-system interfacing Description: Any special requirements regarding interfacing with rest of the system as covered in inputs and outputs sections. 71
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CORBYS Cognitive Control Framework
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D2.1 Requirements and Specification
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D2.1 Requirements and Specification - CORBYS

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