1989_MELPS_7700_Software_Manual

Register Configuration
[Bit-S] Data Length Selection Flag (rn)
This flag specifies whether to use the 16-bit data length or the 8-bit data length. "0" specifies
16-bit, and "1" specifies 8-bit data length. This flag can be set by the SEM and SEP, and cleared
by the CLM and CLP instructions.
[Bit-S] Overflow Flag (V)
The overflow flag has a meaning when adding or subtracting 1 word as a signed binary number.
This flag is set 1 when the flag m is set to "0" and the result of addition or subtraction is outside
the range -32768-+32767, and it is set 0 otherwise. When the flag m is set to "1 ", this flag is
set 1 if the result of addition or subtraction is outside the range -128-+127 and set Ootherwise.
This flag can be directly set by the SEP, and cleared by the CLV and CLP instructions. This flag
is meaningless in the decimal operation mode.
[Bit-7] Negative flag (N)
The negative flag (N) is set 1 when the result of data transfer is negative (bit-15 of data is "1"
when the flag m is "0", or bit-7 of data is "1" when the flag m is "1 "), and it is set 0 otherwise.
This flag can be directly set by the SEP, and cleared by the CLP instructions. This flag is
meaningless in the decimal operation mode.
[Bit-8-BiHO] Processor interrupt priority level (IPLo-IPL2)
The processor interrupt priority level (IPL) consists of 3 bits, and these 3 bits enable determination
of 8 processor interrupt priority levels (Ievel-O - level-7). An interrupt is allowed only when its
interrupt priority level is higher than the IPL value. When an interrupt is generated, IPL is saved
to the stack area, and the priority level of the allowed interrupt is set in IPL.
There is no instruction that can directly set or clear IPLo-IPL2. Therefore, in order to alter the
IPL contents, the desired value must be first stored in the stack and then the processor status
register contents altered using the PUL or PLP instruction.
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