1989_MELPS_7700_Software_Manual

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ClM Clear m Flag ClMOperationmf-ODescription Clears the data length selection flag m to O.Status flagsIPL:NNot affected.Not affected.V Not affected.m Cleared to O.x Not affected.DIZCNot affected.Not affected.Not affected.Not affected.Addressing mode Syntax Machine code Bytes CyclesImplied elM 0816 1 277
CLPClear Processor StatusCLPOperationDescriptionPSL (- PSL /\ IMM(IMM is the immediate value. Its specified in the second byte of the instruction.)Clears the processor status flags specified by the bit pattern in the second byteof the instruction to O.Status flagsThe specifed flags are cleared. IPL is not affected.Addressing mode Syntax Machine code Bytes CyclesImmediate CLP #imm C216, imm 2 478
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MITSUBISHI SEMICONDUCTORSMELPS 7700
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ContentsContents1. Introduction of
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Register Configuration2. Register C
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Register Configuration2.4 Stack Poi
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Register Configuration2.9 Processor
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Addressing Modes3. Addressi ng Mode
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ImmediateModeFunctionImmediate addr
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DirectModeFunctionDirect addressing
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Direct Indexed XModeFunctionDirect
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Direct Indexed YModeFunctionDirect
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D;,rect Indexed X IndirectModeFunct
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Direct Indexed X Indirectex.: Mnemo
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Direct Indirect Indexed Yex.: Mnemo
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Direct Indirect LongModeFunctionDir
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Page 33 and 34: AbsoluteModeFunctionAbsolute addres
Page 35 and 36: Absolute BitModeFunctionAbsolute bi
Page 37 and 38: Absolute Indexed Xex.: MnemonicAOC
Page 39 and 40: Absolute Indexed Yex.: MnemonicLOX
Page 41 and 42: Absolute Long Indexed XModeFunction
Page 43 and 44: Absolute Indirect LongModeFunctionI
Page 45 and 46: StackModeFunctionStack addressing m
Page 47 and 48: RelativeModeFunctionRelative addres
Page 49 and 50: Direct Bit Relativeex.: Mnemonic Ma
Page 51 and 52: Absolute Bit Relativeex. : Mnemonic
Page 53 and 54: Stack Pointer Relative Indirect Ind
Page 55 and 56: Block TransferModeFunctionBlock tra
Page 57 and 58: Instructions4. Instructions4.1 Inst
Page 59 and 60: Instructions4.1.2 Arithmetic Instru
Page 61 and 62: InstructionsCategory Instruction De
Page 63 and 64: InstructionsThe table below lists t
Page 65 and 66: AND logical AND ANDOperation Acc f-
Page 67 and 68: BBC Branch on Bit Clear BBCOperatio
Page 69 and 70: BeeBranch on Carry ClearBeeOperatio
Page 71 and 72: BEQBranch on EqualBEQOperationWhen
Page 73 and 74: BNEBranch on Not EqualBNEOperationW
Page 75 and 76: BRABranch AlwaysBRAOperationFor sho
Page 77 and 78: eveBranch on Overflow CleareveOpera
Page 79 and 80: CLBClear BitCLBOperationM (- MA IMM
Page 81: ,Cli Clear Interrupt Disable Status
Page 85 and 86: CMP Compare CMPOperationAcc - MDesc
Page 87 and 88: CpyCompare Memory and Index Registe
Page 89 and 90: DEXDecrement Index Register X by On
Page 91 and 92: DIV Divide DIVOperationB(remainder}
Page 93 and 94: EOR Exclusive OR Memory with Accumu
Page 95 and 96: INX Increment Index Register X by O
Page 97 and 98: JMPJumpJMPOperationIf absolute addr
Page 99 and 100: LOA Load Accumulator from Memory LO
Page 101 and 102: LOT Load Immediate to Data Bank Reg
Page 103 and 104: LOYLoad Index Register Y from Memor
Page 105 and 106: MPYMultiplyMPYOperationB, A b A x M
Page 107 and 108: MVP Move Positive MVPOperationMn-k
Page 109 and 110: ORA OR Memory with Accumulator ORAO
Page 111 and 112: PElPush Effective Indirect AddressP
Page 113 and 114: PHAPush Accumulator A on StackPHAOp
Page 115 and 116: PHDOperationPush Direct Page Regist
Page 117 and 118: PHPPush Processor Status on StackPH
Page 119 and 120: PHXPush Index Register X on StackPH
Page 121 and 122: PLAPull Accumulator A from StackPLA
Page 123 and 124: PLDOperationPull Direct Page Regist
Page 125 and 126: PLTPull Data Bank Register from Sta
Page 127 and 128: PLYPull Index Register Y from Stack
Page 129 and 130: PSHPushPSHM(8) f- OPRH8 f- 8-1M(8)
Page 131 and 132: PULPullPULSf- S+1PSL f- M(S)Sf- S+1
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ROL Rotate One Bit Left ROLOperatio
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RTIReturn from InterruptRTIOperatio
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RTSReturn from SubroutineRTSOperati
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SEBSet BitSEBOperationM f- M V IMMI
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SEI Set Interrupt Disable Status SE
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SEPSet Processor StatusSEPOperation
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STPStopSTPOperationDescriptionStop
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STYStore Index Register Y in Memory
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lASTransfer Accumulator A to Stack
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TAYTransfer Accumulator A to Ind~x
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TBSTransfer Accumulator B to Stack
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TBvTransfer Accumulator B to Index
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TOBTransfer Direct Page Register to
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TSBTransfer Stack Pointer to Accumu
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TXATransfer Index Register X to Acc
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TXSTransfer Index Register X to Sta
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TVATransfer Index Register Y to Acc
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TYXTransfer Index Register Y to XTY
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XABExchange Accumulator A and 8XABO
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Notes for Programming(11) The code
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Instruction Execution Sequence6.2 C
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Instruction Execution SequenceIE)·
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Instruction Execution Sequence{Exam
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Instruction Execution Sequence(Exam
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Instruction Execution SequenceWhen
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Instruction Execution SequenceOpera
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Instruction Execution SequenceOpera
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APPENDIX ACPU Instruction Execution
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ImpliedInstruction :CLC. CLI. CLM.
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ImpliedInstructionR T STiming¢I CP
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ImpliedInstructionBRKTiming00194
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ImmediateInstruction :. L D TTiming
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ImmediateInstructionDIV, MPYTimingr
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DirectInstructionADC, AND, CMP, CPX
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DirectInstructionDIV, MPYTiming~cpu
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Direct Indexed XInstructionADC, AND
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Direct Indexed XInstructionDIV. MPY
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Direct IndirectInstructionADC. AND.
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Direct Indexed X IndirectInstructio
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Direct Indirect Indexed YInstructio
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Direct Indirect LongInstructionADC,
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Direct Indirect Long Indexed YInstr
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AbsoluteInstructionADC, AND, CMP, C
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AbsoluteInstructionDIV, MPYTimingt/
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Absolute BitInstruction : C L B, S
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Absolute Indexed XInstruction : A S
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Absolute Indexed XAbsolute Indexed
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Absolute LongInstructionAD C, AND,
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Absolute LongInstructionJ M PTiming
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Absolute Long Indexed XInstructionD
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Absolute Indirect LongInstructionJ
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StackInstructionPEA. Timing¢CPUAp(
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StackInstructionP H BTiming4tcpuAp(
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StackInstructionPLPTimingAp(cpu)DAT
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StackInstructionPULTimingPSDATA{Cpu
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Direct Bit RelativeInstructionBBG,
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Stack Pointer RelativeInstruction :
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Stack Pointer Relative Indirect Ind
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Block TransferInstructionMVNTimingI
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APPENDIX BSeries MELPS 7700 Machine
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APPENDIX 8Series MELPS 7700 Machine
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APPENDIX CSeries MELPS 7700 Instruc
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APPENDIX CSeries MELPS 7700 Instruc
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MITSUBISHI SEMICONDUCTORSMELPS 7700
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1989_MELPS_7700_Software_Manual

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