1989_MELPS_7700_Software_Manual

Instruction Execution Sequence
Example 1. ASL instruction / direct addressing mode (OPRL = 0016)
<pepu based CPU instruction execution sequence
¢ CPU
Ap(cPU)
-:/ PG X PG X
AHAL(CPU) ~ PC
X ~ PC+1 _____ D_P_R_H_,_d_d ____ ~X PC+2
X
~
DATA(cPU)
R / W(CPU)
Note: All the signals are CPU internal signals, which cannot be observed from outside.
The following examples 1-1 to 1-6 are examples of the <!>cpu based instruction execution sequences
under various conditions.
Example 1-1
When the instruction queue buffer is vacant
Example 1-2 When two data are in the instruction queue buffer
Example 1-3 When three data are in the instruction queue buffer
Example 1-4 When 16-bit data is accessed from odd address
Example 1-5 When external memory is accessed from the BYTE terminal using 8-bit
external bus width
Example 1-6 When external memory is accessed with wait by the wait bit
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