1989_MELPS_7700_Software_Manual

Instruction Execution Sequence
Operation of the CPU and bus interface unit under various cycles
$No. CPU Bus interface unit
:
1 (No fetching can be done, because there are Fetches the instruction, because instruction queue
2 no operation codes in the instruction queue buffer is vacant and the CPU is not using the bus.
buffer.)
3 ~ Fetches 2 bytes w~th of data into the instruction
4
/
queue bLlffer when E becomes "L".
Fetches the operation code.
5 Fetches operand (dd). Prefetches the instruction because the instruction
6 queue buffer is vacant and the CPU is not using the
bus.
7 (Waits till the bus used by the bus interface Fetches 2 bytes worth of data into the instruction
8 unit becomes vacant.) queue buffer when becomes "L".
g
10
Waits till E becomes "L" to write data.
11 Reads data when E becomes "L".
12
13 Modifies data.
14 Writes data into the data buffer.
-
15 Fetches the next operation code.
16 ? Writes the contents of the data buffer into the original
address (odd address), when E becomes "L".
Note. At the <- - -> part
* When the CPU does not use the bus, $cpu corresponds with $.
* When the CPU uses the bus, the $cpu extends till the writing in the bus interface unit completes. (the $16 to
$17 cycle)
The conditions are the same, except when wait is commanded by the wait bit (example 1-1). When accessing to
the external memory, the cycle of enable output E becomes twice that for no-wait, and thus the <j>cpu wait time
also becomes twice the cycle. ($3 to 1j>4, $7 to $8, $11 to $12, $16 to $17 cycle)
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