1989_MELPS_7700_Software_Manual

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Notes for Programming5. Notes for ProgrammingTake care of the following when programming with the MELPS 7700 series.(1) The stack pointer S is undefined immediately after the reset is commanded. Always set theinitial value.Example)LOX #27FHTXS(2) The program bank register PG and the data bank register DT are disabled under the single chipmode. Do not set value other than "OOlS" here.(3) When "1" is set in the D-flag for decimal operation:The C-flag alone is effective in the ADC instruction, while the Z, N, and V flags are disabled.The C and Z flags alone are effective in the SBC instruction, while the N and V flags aredisabled. (Decimal operation can be done in the ADC and the SBC instructions alone.)(4) Using the 16-bit immediate data with "1" (data length: 8 bits) in the data length selection flagm, or using the 8- bit immediate data with "0" (data length: 16 bits) in flag m, will cause theprogram run-away. The same rule is applied to the index register length selection flag x. Takecare of the condition of these flags when coding the program.(5) The MELPS 7700 can prefetch the instructions using the 3-byte instruction queue buffer. Keepin mind when creating the timer with the software, that the number of cycles shown in the listof machine language instructions is the minimum value. (Also see Chapter 6.)(6) When value other than "OOlS" is set in the lower order 8 bits of the direct page register DPR(DPRL), the processing time will become 1 machine cycle longer than when "OOlS" is set.(7) The processing speed will deteriorate if a 16- bit data will be accessed from an odd address.Place the 16-bit data from an even address if the processing speed is important.(8) The Nand Z flags will change by execution of the PLA instruction, but the contents of the processorstatus register will not change if the accumulator A alone is recovered by the PUL instruction.(9) The program bank register PG can be saved into the stack by setting "1" in bit 6 of the operationby the PSH instruction. However, the PG cannot be recovered by the PUL instruction.(10) When the PUL or the PSH instruction is executed, the flag m and the flag x are affected inaddition.165
Notes for Programming(11) The code in the second byte of the BRK instruction will not affect the CPU.(12) When the block transfer instruction (MVN or MVP) is executed with x=1, the contents of middleorder 8-bit in source and destination address (There are consists of 24-bit.) will be fixed "0016".166
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MITSUBISHI SEMICONDUCTORSMELPS 7700
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ContentsContents1. Introduction of
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Register Configuration2. Register C
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Register Configuration2.4 Stack Poi
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Register Configuration2.9 Processor
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Addressing Modes3. Addressi ng Mode
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ImmediateModeFunctionImmediate addr
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DirectModeFunctionDirect addressing
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Direct Indexed XModeFunctionDirect
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Direct Indexed YModeFunctionDirect
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D;,rect Indexed X IndirectModeFunct
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Direct Indexed X Indirectex.: Mnemo
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Direct Indirect Indexed Yex.: Mnemo
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Direct Indirect LongModeFunctionDir
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Direct Indirect Long Indexed Yex.:
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AbsoluteModeFunctionAbsolute addres
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Absolute BitModeFunctionAbsolute bi
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Absolute Indexed Xex.: MnemonicAOC
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Absolute Indexed Yex.: MnemonicLOX
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Absolute Long Indexed XModeFunction
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Absolute Indirect LongModeFunctionI
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StackModeFunctionStack addressing m
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RelativeModeFunctionRelative addres
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Direct Bit Relativeex.: Mnemonic Ma
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Absolute Bit Relativeex. : Mnemonic
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Stack Pointer Relative Indirect Ind
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Block TransferModeFunctionBlock tra
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Instructions4. Instructions4.1 Inst
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Instructions4.1.2 Arithmetic Instru
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InstructionsCategory Instruction De
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InstructionsThe table below lists t
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AND logical AND ANDOperation Acc f-
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BBC Branch on Bit Clear BBCOperatio
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BeeBranch on Carry ClearBeeOperatio
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BEQBranch on EqualBEQOperationWhen
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BNEBranch on Not EqualBNEOperationW
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BRABranch AlwaysBRAOperationFor sho
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eveBranch on Overflow CleareveOpera
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CLBClear BitCLBOperationM (- MA IMM
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,Cli Clear Interrupt Disable Status
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CLPClear Processor StatusCLPOperati
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CMP Compare CMPOperationAcc - MDesc
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CpyCompare Memory and Index Registe
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DEXDecrement Index Register X by On
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DIV Divide DIVOperationB(remainder}
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EOR Exclusive OR Memory with Accumu
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INX Increment Index Register X by O
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JMPJumpJMPOperationIf absolute addr
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LOA Load Accumulator from Memory LO
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LOT Load Immediate to Data Bank Reg
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LOYLoad Index Register Y from Memor
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MPYMultiplyMPYOperationB, A b A x M
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MVP Move Positive MVPOperationMn-k
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ORA OR Memory with Accumulator ORAO
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PElPush Effective Indirect AddressP
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PHAPush Accumulator A on StackPHAOp
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PHDOperationPush Direct Page Regist
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PHPPush Processor Status on StackPH
Page 119 and 120: PHXPush Index Register X on StackPH
Page 121 and 122: PLAPull Accumulator A from StackPLA
Page 123 and 124: PLDOperationPull Direct Page Regist
Page 125 and 126: PLTPull Data Bank Register from Sta
Page 127 and 128: PLYPull Index Register Y from Stack
Page 129 and 130: PSHPushPSHM(8) f- OPRH8 f- 8-1M(8)
Page 131 and 132: PULPullPULSf- S+1PSL f- M(S)Sf- S+1
Page 133 and 134: ROL Rotate One Bit Left ROLOperatio
Page 135 and 136: RTIReturn from InterruptRTIOperatio
Page 137 and 138: RTSReturn from SubroutineRTSOperati
Page 139 and 140: SEBSet BitSEBOperationM f- M V IMMI
Page 141 and 142: SEI Set Interrupt Disable Status SE
Page 143 and 144: SEPSet Processor StatusSEPOperation
Page 145 and 146: STPStopSTPOperationDescriptionStop
Page 147 and 148: STYStore Index Register Y in Memory
Page 149 and 150: lASTransfer Accumulator A to Stack
Page 151 and 152: TAYTransfer Accumulator A to Ind~x
Page 153 and 154: TBSTransfer Accumulator B to Stack
Page 155 and 156: TBvTransfer Accumulator B to Index
Page 157 and 158: TOBTransfer Direct Page Register to
Page 159 and 160: TSBTransfer Stack Pointer to Accumu
Page 161 and 162: TXATransfer Index Register X to Acc
Page 163 and 164: TXSTransfer Index Register X to Sta
Page 165 and 166: TVATransfer Index Register Y to Acc
Page 167 and 168: TYXTransfer Index Register Y to XTY
Page 169: XABExchange Accumulator A and 8XABO
Page 173 and 174: Instruction Execution Sequence6.2 C
Page 175 and 176: Instruction Execution SequenceIE)·
Page 177 and 178: Instruction Execution Sequence{Exam
Page 179 and 180: Instruction Execution Sequence(Exam
Page 185 and 186: Instruction Execution SequenceWhen
Page 187 and 188: Instruction Execution SequenceOpera
Page 189 and 190: Instruction Execution SequenceOpera
Page 193 and 194: APPENDIX ACPU Instruction Execution
Page 195 and 196: ImpliedInstruction :CLC. CLI. CLM.
Page 197 and 198: ImpliedInstructionR T STiming¢I CP
Page 199 and 200: ImpliedInstructionBRKTiming00194
Page 201 and 202: ImmediateInstruction :. L D TTiming
Page 203 and 204: ImmediateInstructionDIV, MPYTimingr
Page 205 and 206: DirectInstructionADC, AND, CMP, CPX
Page 207 and 208: DirectInstructionDIV, MPYTiming~cpu
Page 209 and 210: Direct Indexed XInstructionADC, AND
Page 211 and 212: Direct Indexed XInstructionDIV. MPY
Page 213 and 214: Direct IndirectInstructionADC. AND.
Page 215 and 216: Direct Indexed X IndirectInstructio
Page 217 and 218: Direct Indirect Indexed YInstructio
Page 219 and 220: Direct Indirect LongInstructionADC,
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Direct Indirect Long Indexed YInstr
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AbsoluteInstructionADC, AND, CMP, C
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AbsoluteInstructionDIV, MPYTimingt/
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Absolute BitInstruction : C L B, S
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Absolute Indexed XInstruction : A S
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Absolute Indexed XAbsolute Indexed
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Absolute LongInstructionAD C, AND,
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Absolute LongInstructionJ M PTiming
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Absolute Long Indexed XInstructionD
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Absolute Indirect LongInstructionJ
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StackInstructionPEA. Timing¢CPUAp(
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StackInstructionP H BTiming4tcpuAp(
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StackInstructionPLPTimingAp(cpu)DAT
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StackInstructionPULTimingPSDATA{Cpu
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Direct Bit RelativeInstructionBBG,
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Stack Pointer RelativeInstruction :
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Stack Pointer Relative Indirect Ind
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Block TransferInstructionMVNTimingI
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APPENDIX BSeries MELPS 7700 Machine
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APPENDIX 8Series MELPS 7700 Machine
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APPENDIX CSeries MELPS 7700 Instruc
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APPENDIX CSeries MELPS 7700 Instruc
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MITSUBISHI SEMICONDUCTORSMELPS 7700
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1989_MELPS_7700_Software_Manual

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