1989_MELPS_7700_Software_Manual

Instruction Execution Sequence
6.3 Instruction Execution Sequence
The instruction execution sequence of the CPU based on the <!>cPu, and the variation of the actual
instruction execution cycle when various conditions are applied are shown here.
• Example 1. ASL instruction
Direct addressing mode
• Example 2. LDA instruction Direct indirect long addressing mode
C:::.::::.:;·:;::.!-: .:>< I Before observing the <!>cPu based CPU instruction execution sequence \'>':;.;:. '.:" v.·.1
The following table describes the <!>cPu based CPU instruction execution sequence symbols. The
signals indicated in this execution sequence are all CPU internal signals, that show data exchange
between the bus interface unit and the CPU. Accordingly, these signals cannot be
observed from outside.
<!>CPu Based CPU Instruction E~ecution Sequence Symbols
Symbol
Description
<!>cpu
Ap(cpu)
AHAL(CPU)
DATA(cpu)
R/W(cpu)
PG,PC
ADp
ADH,ADL
DPRH
OPRL
OH
OL
CPU basic clock
Higher order 8 bits of the address (24 bits) of the program that the CPU is actually execution
Lower order 16 bits of the address (24 bits) of the program that the CPU is actually execution
Data information the CPU is processing
Data read/write request to the data buffer in the bus interface
Contents of the program bank register (PG) and the program counter (PC)
Data indicating the address (higher order B bits)
Data indicating the address (middle order 8 bits, lower order 8 bits)
Contents of the higher order 8 bits of the direct page register
Contents of the lower order B bits of the direct page register (DPRL = 0 in the examples)
Data to be fetched or written from the data buffer by the CPU (higher order 8 bits)
Data to be fetched or written from the data buffer by the CPU (lower order 8 bits)
dd Contents of the operand (DPRL = 0 in examples 1 and 2, so dd represents the lower order 8
bits of the address)
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