1989_MELPS_7700_Software_Manual

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DirectInstructionSTA, STX, STYTimingDPRL oF 0c ;:;.When DPRL=O, this cycle IS nothingInstruction : A S L, DEC, INC, L S R, R 0 L, R 0 RTiming:DPRL oF 0¢CPUDATAICPU)R/WICPu) _ "H"=-====---====--===~===--=:::::;-~~When DPRL =0, this cycle IS nothing201
DirectInstructionDIV, MPYTiming~cpuII_.JOATA(cpu)R/W(cpu) "H"=:"'===~===~===-===-:===~~~IiiWhen OPRL =0, this cycle IS nothing.00 or 01OPR+dd~~u~ Not used X Not used X ~~"6ode )MPY instruction is 12-cycle, and OIV instruction IS 23-cycle.202
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MITSUBISHI SEMICONDUCTORSMELPS 7700
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ContentsContents1. Introduction of
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Register Configuration2. Register C
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Register Configuration2.4 Stack Poi
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Register Configuration2.9 Processor
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Addressing Modes3. Addressi ng Mode
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ImmediateModeFunctionImmediate addr
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DirectModeFunctionDirect addressing
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Direct Indexed XModeFunctionDirect
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Direct Indexed YModeFunctionDirect
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D;,rect Indexed X IndirectModeFunct
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Direct Indexed X Indirectex.: Mnemo
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Direct Indirect Indexed Yex.: Mnemo
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Direct Indirect LongModeFunctionDir
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Direct Indirect Long Indexed Yex.:
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AbsoluteModeFunctionAbsolute addres
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Absolute BitModeFunctionAbsolute bi
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Absolute Indexed Xex.: MnemonicAOC
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Absolute Indexed Yex.: MnemonicLOX
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Absolute Long Indexed XModeFunction
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Absolute Indirect LongModeFunctionI
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StackModeFunctionStack addressing m
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RelativeModeFunctionRelative addres
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Direct Bit Relativeex.: Mnemonic Ma
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Absolute Bit Relativeex. : Mnemonic
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Stack Pointer Relative Indirect Ind
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Block TransferModeFunctionBlock tra
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Instructions4. Instructions4.1 Inst
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Instructions4.1.2 Arithmetic Instru
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InstructionsCategory Instruction De
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InstructionsThe table below lists t
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AND logical AND ANDOperation Acc f-
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BBC Branch on Bit Clear BBCOperatio
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BeeBranch on Carry ClearBeeOperatio
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BEQBranch on EqualBEQOperationWhen
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BNEBranch on Not EqualBNEOperationW
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BRABranch AlwaysBRAOperationFor sho
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eveBranch on Overflow CleareveOpera
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CLBClear BitCLBOperationM (- MA IMM
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,Cli Clear Interrupt Disable Status
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CLPClear Processor StatusCLPOperati
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CMP Compare CMPOperationAcc - MDesc
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CpyCompare Memory and Index Registe
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DEXDecrement Index Register X by On
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DIV Divide DIVOperationB(remainder}
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EOR Exclusive OR Memory with Accumu
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INX Increment Index Register X by O
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JMPJumpJMPOperationIf absolute addr
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LOA Load Accumulator from Memory LO
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LOT Load Immediate to Data Bank Reg
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LOYLoad Index Register Y from Memor
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MPYMultiplyMPYOperationB, A b A x M
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MVP Move Positive MVPOperationMn-k
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ORA OR Memory with Accumulator ORAO
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PElPush Effective Indirect AddressP
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PHAPush Accumulator A on StackPHAOp
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PHDOperationPush Direct Page Regist
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PHPPush Processor Status on StackPH
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PHXPush Index Register X on StackPH
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PLAPull Accumulator A from StackPLA
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PLDOperationPull Direct Page Regist
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PLTPull Data Bank Register from Sta
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PLYPull Index Register Y from Stack
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PSHPushPSHM(8) f- OPRH8 f- 8-1M(8)
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PULPullPULSf- S+1PSL f- M(S)Sf- S+1
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ROL Rotate One Bit Left ROLOperatio
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RTIReturn from InterruptRTIOperatio
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RTSReturn from SubroutineRTSOperati
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SEBSet BitSEBOperationM f- M V IMMI
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SEI Set Interrupt Disable Status SE
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SEPSet Processor StatusSEPOperation
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STPStopSTPOperationDescriptionStop
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STYStore Index Register Y in Memory
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lASTransfer Accumulator A to Stack
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TAYTransfer Accumulator A to Ind~x
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TBSTransfer Accumulator B to Stack
Page 155 and 156: TBvTransfer Accumulator B to Index
Page 157 and 158: TOBTransfer Direct Page Register to
Page 159 and 160: TSBTransfer Stack Pointer to Accumu
Page 161 and 162: TXATransfer Index Register X to Acc
Page 163 and 164: TXSTransfer Index Register X to Sta
Page 165 and 166: TVATransfer Index Register Y to Acc
Page 167 and 168: TYXTransfer Index Register Y to XTY
Page 169 and 170: XABExchange Accumulator A and 8XABO
Page 171 and 172: Notes for Programming(11) The code
Page 173 and 174: Instruction Execution Sequence6.2 C
Page 175 and 176: Instruction Execution SequenceIE)·
Page 177 and 178: Instruction Execution Sequence{Exam
Page 179 and 180: Instruction Execution Sequence(Exam
Page 185 and 186: Instruction Execution SequenceWhen
Page 187 and 188: Instruction Execution SequenceOpera
Page 189 and 190: Instruction Execution SequenceOpera
Page 193 and 194: APPENDIX ACPU Instruction Execution
Page 195 and 196: ImpliedInstruction :CLC. CLI. CLM.
Page 197 and 198: ImpliedInstructionR T STiming¢I CP
Page 199 and 200: ImpliedInstructionBRKTiming00194
Page 201 and 202: ImmediateInstruction :. L D TTiming
Page 203 and 204: ImmediateInstructionDIV, MPYTimingr
Page 205: DirectInstructionADC, AND, CMP, CPX
Page 209 and 210: Direct Indexed XInstructionADC, AND
Page 211 and 212: Direct Indexed XInstructionDIV. MPY
Page 213 and 214: Direct IndirectInstructionADC. AND.
Page 215 and 216: Direct Indexed X IndirectInstructio
Page 217 and 218: Direct Indirect Indexed YInstructio
Page 219 and 220: Direct Indirect LongInstructionADC,
Page 221 and 222: Direct Indirect Long Indexed YInstr
Page 223 and 224: AbsoluteInstructionADC, AND, CMP, C
Page 225 and 226: AbsoluteInstructionDIV, MPYTimingt/
Page 227 and 228: Absolute BitInstruction : C L B, S
Page 229 and 230: Absolute Indexed XInstruction : A S
Page 231 and 232: Absolute Indexed XAbsolute Indexed
Page 233 and 234: Absolute LongInstructionAD C, AND,
Page 235 and 236: Absolute LongInstructionJ M PTiming
Page 237 and 238: Absolute Long Indexed XInstructionD
Page 239 and 240: Absolute Indirect LongInstructionJ
Page 241 and 242: StackInstructionPEA. Timing¢CPUAp(
Page 243 and 244: StackInstructionP H BTiming4tcpuAp(
Page 245 and 246: StackInstructionPLPTimingAp(cpu)DAT
Page 247 and 248: StackInstructionPULTimingPSDATA{Cpu
Page 249 and 250: Direct Bit RelativeInstructionBBG,
Page 251 and 252: Stack Pointer RelativeInstruction :
Page 253 and 254: Stack Pointer Relative Indirect Ind
Page 255 and 256: Block TransferInstructionMVNTimingI
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APPENDIX BSeries MELPS 7700 Machine
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APPENDIX 8Series MELPS 7700 Machine
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APPENDIX CSeries MELPS 7700 Instruc
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APPENDIX CSeries MELPS 7700 Instruc
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MITSUBISHI SEMICONDUCTORSMELPS 7700
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1989_MELPS_7700_Software_Manual

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