1989_MELPS_7700_Software_Manual

Instruction Execution Sequence
Operation of the CPU and bus interface unit under various cycles
<p No. CPU Bus interface unit
1 Fetches operation code.
2 Fetches operand (dd).
3 Waits for E to become "Ln, to read data.
4 Reads data when E becomes "Ln.
5 Modifies data. Prefetches the instruction, because there are two
vacant instruction queue buffers and the CPU is not
using the bus.
6 (Waits till the bus used by the bus interface Fetches 2·byte worth of data into the instruction
unit becomes vacant.)
queue buffer when to becomes "Ln.
7 Writes data into the data buffer.
8 Fetches the next operation code. Writes the contents of the data buffer into the origi·
nal address, as E becomes "Ln.
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