1989_MELPS_7700_Software_Manual

Instruction Execution Sequence
6.2 Change of the CPU Basic Clock <!>cPu
When the bus interface unit is not ready, the CPU extends the basic clock to synchronize with
the bus, and waits till it is ready. As the CPU basic clock waits owing to some conditions, this
clock will be called <jlcpu to be distinguished from the clock. The following are the cases in which
the cj>cpu waits.
Causes for the <!>cPu to wait
<Cause 1>
When the CPU requests operation codes and operands, but the operation codes and operands
in the instruction queue buffer did not reach the necessary number.
<Cause 2>
When the CPU tried to access data, but the bus interface unit was using the bus for fetching
some data into the instruction queue buffer or writing data.
<Cause 3>
When the bus interface unit was reading data from the internallexternal memory or liD,
according to the request of the CPU.
In addition to the above, the following are also causes for the cj>cpu to be extended.
• When 16-bit data is accessed from odd address .
• When external memory 16-bit data is accessed while the BYTE terminal level is "H" .
• When external memory is accessed with wait commanded by the wait bit.
The above conditions causes the execution time to differ each time, even with the same instruction
and same addressing mode. Two example instructions are given in the next section to see
th~ variation of the number of cycles according to the above conditions.
The" CPU execution sequence per addressing mode " of Appendix-A is the CPU instruction
execution sequences based on the cj>cpu. The number of cycles shown in " 4.2 Instructions" and
" Appendix-B List of machir1e language instructions" are the count for the shortest case, and
cannot always be applied when calculating the actual cycles or the execution time of instructions.
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