1989_MELPS_7700_Software_Manual

Instruction Execution Sequence
(Example 2-1) When the internal as well as the external memories are used together while wait
is commanded by the wait bit.
Conditions
• Number of data in the instruction queue buffer
• Bank 0
Bank 1 and after
• Data length selection flag m
• BYTE terminal level
• Contents of lower order bytes (PCL) of the program counter
• Contents of the operand (dd)
• Data indicated by the address ADL
ADp
o
Internal ROM, RAM are used
External memory is used
"0" (16-bit length)
"L" (External bus width is 16 bits)
Even
Even
Even
1 or more (bank 1 and after)
<!> based execution sequence
2
3 4
5
6
7 8 9
10 11 12
13 14
<jlcpu
Number of data in
Instruction queue
buffer
~ Fetches Op
1 Code
i
2-.1
Fetches
Operand
o
2
Reads
Data
Calculates
Address
Reads
Data
Reads
Data
~g;~:(.ven)~~---"o..:.o_~)@0<
ADp
X
'j Op Code Next Op Code ~--~
A'S-AiJ
i
IDATA(odd) ~ DPF+l 'I:D.. ADH
X
, Opel and (dd) ~ __----J
I
!
ADL
A7-Ao =:X_---'-_-'X 11+2 X,-__
;
do..;.d __ -,X dd+2 Xr-----'---~
DL
DH
Next
' InstrUction
x:=
t=
t=
~
R/W
"H" i~-------------------------------
Cause for $cPU to queue ~
Cause 1
~
Cause 2
~
Cause 3
~
Cause 3 Cause 3
186