1989_MELPS_7700_Software_Manual

PUL
Operation
Pull
M(S) -4 A, B, X, Y, DPR, DT or PS
PUL
Description
This instruction's second byte specifies the registers to be restored. The registers
corresponding to the bits in the second byte that are 1 are restored from the
stack. The bit and register correspondence is as shown below:
PS I DT I DPR I Y X B A
bo
Restored from the stack in this order. -t
(Note) The contents of accumulator B's higher S-bit will be changed, when PUL instruction
is executed with m=O and the restored registor including PS whose m=1.
Status flags
When bit 7 of the instruction's second byte is 1, specifying that the program
status register PS is to be restored, the status flags are restored to the values
that had been restored from the stack. Otherwise, the status flags are not
affected.
Addressing mode Syntax Machine code Bytes Cycles
Stack PUL #nn FB16, nn 2 14+3xi1+4xi2
(Note1) To the cycles-count shown above, the values shown below are added depending on the registers
being restored. The count is 14 cycles when no registers are restored. h in above table represents
the number of registers (chosen from A, B, X, Y, PS and OT) to be saved. i2=1 if OPR is to be
restored, and i2=0 if OPR is not to be restored.
125