1989_MELPS_7700_Software_Manual

Instruction Execution Sequence
Operation of the CPU and bus interface unit under various cycles
<jJNo. CPU Bus interface unit
1 Fetches operation code.
2 Fetches operand (dd). Prefetches the instruction, because the instruct
queue buffer is vacant and the CPU is not using
the bus.
3 (Waits till the bus used by the bus interface unit Fetches 2-byte worth of data into the instruction
becomes vacanl.)
queue buffer when E becomes "L".
4 Waits for E to become "L", to read data.
5 Reads data when E becomes "Ln.
6 Modifies data.
7 Writes data into the data buffer.
S Fetches the next operation code. Writes the contents of the data buffer into the
original address, when E becomes "Ln.
175