1989_MELPS_7700_Software_Manual

Instruction Execution Sequence
Operation of the CPU and bus interface unit under various cycles
IjlNo. CPU Bus Interface unit
1 (No fetching can be done, because there are Fetches the instruction, because instruction queue
no operation codes in the instruction queue buffer is vacant and the CPU is not using the bus.
buffer.)
2
Fetches operation code.
~
Fetches 1 odd address byte worth of data into the
instruction queue buffer, when E becomes--"L".
3 (No fetching can be done, because there are Fetches the instruction, because instruction queue
no operands in the instruction queue buffer.) buffer is vacant and the CPU is not using the bus.
4
Fetches operand (dd).
~
Fetches 2-byte worth of data into the instruction
queue buffer when E becomes "L".
5 Waits for E to become "L", to read data.
6 Reads data in the odd addresses (OL) alone into the data buffer when E becomes "L".
7 Waits for E to become "L", to read data.
8 Reads data in the even addresses (OH) alone into the data buffer when E becomes "L".
9 Modifies data. Prefetches the instruction, because there are two
vacant positions in the instruction queue buffer,
and the CPU is not using the bus.
10 (Waits till the bus used by the bus interface Fetches 2 bytes worth of data into the instruction
unit becomes vacant.)
queue buffer, when E becomes "L".
11 Writes data into the data buffer. Waits till E becomes "L" to write data.
12 Fetches the next operation code. Writes the contents of the data buffer (OL) into the
original address (odd address), when 1: becomes
"L".
13 ? Waits till E becomes "L" to write data.
14 Writes the contents of the data buffer (OH) into the
? original address (even address), when E becomes
"L".
When internal ROM or BYTE terminal level "L" external memory is used as the program memory, the instruction is
fetched into the instruction queue buffer normally in 2-byte (word) unit of sequential even and odd addresses in this
order. However, when the instruction must be fetched from odd address like after execution of the JMP instruction,
the 1-byte of the first odd address alone is fetched into the instruction queue buffer ($2 cycle), and the later instructions
are fetched into the instruction queue buffer in 2-byte units (<1>4, $10 cycle).
The bus interface unit automatically selects whether to fetch one word or to fetch the 1 byte of odd address alone.
The operation status can be observed from outside, according to the output of the BHE terminal and the address bus
signal Ao, as long as the mode is not single chip mode .
• When one word is fetched
The output from both the BHE terminal and the address bus Ao are at the "L" level.
• When 1 byte of odd address alone is fetched
The output from the BHE terminal is "L", while the output from address bus Ao is "H".
179