1989_MELPS_7700_Software_Manual

o Jperation 0 f t h e CPU an db us mter ace un t un d er var ous eye es
Instruction Execution Sequence
cjlNo. CPU Bus interface unit
1 (No fetching can be done, because there are no Fetches the instruction, because instruction queue
operation codes in the instruction queue buffer.) buffer is vacant and the CPU is not using the bus.
2 Fetches 2 bytes worth of data into the instruction
,./ queue buffer when E becomes "L".
Fetches the operation code.
3 Fetches operand (dd). Prefetches the instruction because the instruction
queue buffer is vacant and the CPU is not using the
bus.
4 (Waits till the bus used by the bus interface unit Fetches 2 bytes worth of data into the instruction
becomes vacant.)
queue buffer when E becomes "L".
5 Waits for E to becomes "L", to read data (ADH ADL) indicated by the address obtained by adding the
contents of the operand (dd) and the DPRL.
6 Reads data when E becomes "L".
7 Calculated address.
8 Waits for E to become "L", to read data (ADp).
9 Reads data when E becomes "L".
10 Waits for E to become "Ln, to read the data (DH DL) at the address specified by ADp ADH ADL.
11
12 Reads data when E becomes "Ln.
13
The above is the case when bank 1 and after are used by the external memory under the memory expansion mode.
The currently executed program is in bank O. The contents of the lower order bytes of the direct page register DPRL
is "0016", so the direct pages are all in bank O. The access to the outside (cjllO to cjl13 cycle) alone is affected by the
wait bit, and access to the internal memory is not affected by the bit.
187