1989_MELPS_7700_Software_Manual

Instruction Execution Sequence
(Example 1-5)
When external memory is accessed from the BYTE terminal using
a-bit external bus width
Conditions
• Number of data in the instruction queue buffer
• ROM, RAM
• Data length selection flag m
• BYTE terminal level
• Contents of lower order bytes (PCl) of the program counter
• Contents of the operand (dd)
o
External memory is used
"0" (16-bit length)
"H" (External bus width is 8 bits)
Even
Even
<jJ based execution sequence
,1 2
3 4
5 6 7 8 9
10 11 12 13 14
<j)cpu
Number of data In
mstructlon queue
butler
Fetches Op
Code
Fetches
Operand
1-,0
Reads Data
A'5-Aa ,~--____ ,.---____ ,.---------,
mm
DPR-<
I DATA(odd) =x mm X X
X
11+1
X
dd
X dd+1
X
Modifies Wntes ; Next
Data Data ~ Instruction
0
Modified Dl
Modified DH
mm
X . DPR-< x=
11+2
X dd X dd+1 x=
RIW
Cause for ¢CPU 10 queue ~
Cause 1
~
Cause 1
..
Cause 3
~
~_--JI
~----___ ---II
Cause 2
Cause 2 (Note)
~ .......
Note. At the <- - -> part
* When the CPU does not use the bus, ¢cpu corresponds with ¢.
* When the CPU uses the bus, the <jJcpu queues till the writing In the bus interface unit completes. (the <jJ13 to <jJ14
cycle)
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