1989_MELPS_7700_Software_Manual

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Direct Bit RelativeModeFunctionDirect bit relative addressing modeSpecifies the bank-O memory location by the value obtained by adding the instruction'ssecond byte to the direct page register's contents, and specifies the positionsof multiple bits in the memory location by the bit pattern in the third and fourth bytes(the third byte only if the m flag is set to 1). Then, if the specified bits all satisfy thebranching conditions, the instruction's fifth byte (or the fourth byte if the m flag is setto 1) is added to the program counter as a signed value, generating the branchingdestination address. If, however, addition of the instruction's second byte to the directpage register's contents result in a value that exceeds the bank-O range, the specifiedlocation will be in bank-1.Instruction: BBG, BBSex.: Mnemonic Machine CodeBBS j:l:SAH, 04H, OF6H 24'604'6 SA'6 F6'6(m=1)MemoryMemory011111111101111001238"Bank-O------r-------Address to b eexecuted next(r-------ProgramBank Register11,. FFFD,.-------Jump\Op Code (24,,)Operand (04,.)Operand (SA,,)Operand (F6,.)-( Branch)Direct PageRegister+ 11234,.1 = 1238,.ProgramBank Register~0007,.Address to beexecuted nextOp Code (24,.)Operand (04,,)Operand (SA,.)Operand (F6,.)- -(N ot branch)Direct PageRegister+ 11234,.1=1238"ProgramBank Register~ 0007,.43
Direct Bit Relativeex.: Mnemonic Machine CodeBBS :15AA5H, 04H, OF6H 24'604'6 A5'6 5A'6 F6'6(m=O)MemoryMemory111111010111111011101111101111001238"001238,.Bank-O1------Address to beexecuted nextlr-------ProgramBank Register~ FFFE,.-------Jump\Op Code (24,.)Operand (04,,)Operand (AS,,)Operand (SA,.)Operand (!'~Direct PageRegister+ 11234,,1= 1238,.ProgramBank Register~ 0008,.Address to beexecuted nextOp Code (24,.)Operand (04,,)Operand (AS,.)Operand (SA,.)Operand (F6,,)Direct Pag,eRegister+ 11234,.1= 1238"ProgramBank Register~0008,.( Branch)(Not branch)44
Page 1 and 2: MITSUBISHI SEMICONDUCTORSMELPS 7700
Page 4: ContentsContents1. Introduction of
Page 7 and 8: Register Configuration2. Register C
Page 9 and 10: Register Configuration2.4 Stack Poi
Page 11 and 12: Register Configuration2.9 Processor
Page 13 and 14: Addressing Modes3. Addressi ng Mode
Page 15 and 16: ImmediateModeFunctionImmediate addr
Page 17 and 18: DirectModeFunctionDirect addressing
Page 19 and 20: Direct Indexed XModeFunctionDirect
Page 21 and 22: Direct Indexed YModeFunctionDirect
Page 23 and 24: D;,rect Indexed X IndirectModeFunct
Page 25 and 26: Direct Indexed X Indirectex.: Mnemo
Page 27 and 28: Direct Indirect Indexed Yex.: Mnemo
Page 29 and 30: Direct Indirect LongModeFunctionDir
Page 31 and 32: Direct Indirect Long Indexed Yex.:
Page 33 and 34: AbsoluteModeFunctionAbsolute addres
Page 35 and 36: Absolute BitModeFunctionAbsolute bi
Page 37 and 38: Absolute Indexed Xex.: MnemonicAOC
Page 39 and 40: Absolute Indexed Yex.: MnemonicLOX
Page 41 and 42: Absolute Long Indexed XModeFunction
Page 43 and 44: Absolute Indirect LongModeFunctionI
Page 45 and 46: StackModeFunctionStack addressing m
Page 47: RelativeModeFunctionRelative addres
Page 51 and 52: Absolute Bit Relativeex. : Mnemonic
Page 53 and 54: Stack Pointer Relative Indirect Ind
Page 55 and 56: Block TransferModeFunctionBlock tra
Page 57 and 58: Instructions4. Instructions4.1 Inst
Page 59 and 60: Instructions4.1.2 Arithmetic Instru
Page 61 and 62: InstructionsCategory Instruction De
Page 63 and 64: InstructionsThe table below lists t
Page 65 and 66: AND logical AND ANDOperation Acc f-
Page 67 and 68: BBC Branch on Bit Clear BBCOperatio
Page 69 and 70: BeeBranch on Carry ClearBeeOperatio
Page 71 and 72: BEQBranch on EqualBEQOperationWhen
Page 73 and 74: BNEBranch on Not EqualBNEOperationW
Page 75 and 76: BRABranch AlwaysBRAOperationFor sho
Page 77 and 78: eveBranch on Overflow CleareveOpera
Page 79 and 80: CLBClear BitCLBOperationM (- MA IMM
Page 81 and 82: ,Cli Clear Interrupt Disable Status
Page 83 and 84: CLPClear Processor StatusCLPOperati
Page 85 and 86: CMP Compare CMPOperationAcc - MDesc
Page 87 and 88: CpyCompare Memory and Index Registe
Page 89 and 90: DEXDecrement Index Register X by On
Page 91 and 92: DIV Divide DIVOperationB(remainder}
Page 93 and 94: EOR Exclusive OR Memory with Accumu
Page 95 and 96: INX Increment Index Register X by O
Page 97 and 98: JMPJumpJMPOperationIf absolute addr
Page 99 and 100:
LOA Load Accumulator from Memory LO
Page 101 and 102:
LOT Load Immediate to Data Bank Reg
Page 103 and 104:
LOYLoad Index Register Y from Memor
Page 105 and 106:
MPYMultiplyMPYOperationB, A b A x M
Page 107 and 108:
MVP Move Positive MVPOperationMn-k
Page 109 and 110:
ORA OR Memory with Accumulator ORAO
Page 111 and 112:
PElPush Effective Indirect AddressP
Page 113 and 114:
PHAPush Accumulator A on StackPHAOp
Page 115 and 116:
PHDOperationPush Direct Page Regist
Page 117 and 118:
PHPPush Processor Status on StackPH
Page 119 and 120:
PHXPush Index Register X on StackPH
Page 121 and 122:
PLAPull Accumulator A from StackPLA
Page 123 and 124:
PLDOperationPull Direct Page Regist
Page 125 and 126:
PLTPull Data Bank Register from Sta
Page 127 and 128:
PLYPull Index Register Y from Stack
Page 129 and 130:
PSHPushPSHM(8) f- OPRH8 f- 8-1M(8)
Page 131 and 132:
PULPullPULSf- S+1PSL f- M(S)Sf- S+1
Page 133 and 134:
ROL Rotate One Bit Left ROLOperatio
Page 135 and 136:
RTIReturn from InterruptRTIOperatio
Page 137 and 138:
RTSReturn from SubroutineRTSOperati
Page 139 and 140:
SEBSet BitSEBOperationM f- M V IMMI
Page 141 and 142:
SEI Set Interrupt Disable Status SE
Page 143 and 144:
SEPSet Processor StatusSEPOperation
Page 145 and 146:
STPStopSTPOperationDescriptionStop
Page 147 and 148:
STYStore Index Register Y in Memory
Page 149 and 150:
lASTransfer Accumulator A to Stack
Page 151 and 152:
TAYTransfer Accumulator A to Ind~x
Page 153 and 154:
TBSTransfer Accumulator B to Stack
Page 155 and 156:
TBvTransfer Accumulator B to Index
Page 157 and 158:
TOBTransfer Direct Page Register to
Page 159 and 160:
TSBTransfer Stack Pointer to Accumu
Page 161 and 162:
TXATransfer Index Register X to Acc
Page 163 and 164:
TXSTransfer Index Register X to Sta
Page 165 and 166:
TVATransfer Index Register Y to Acc
Page 167 and 168:
TYXTransfer Index Register Y to XTY
Page 169 and 170:
XABExchange Accumulator A and 8XABO
Page 171 and 172:
Notes for Programming(11) The code
Page 173 and 174:
Instruction Execution Sequence6.2 C
Page 175 and 176:
Instruction Execution SequenceIE)·
Page 177 and 178:
Instruction Execution Sequence{Exam
Page 179 and 180:
Instruction Execution Sequence(Exam
Page 181 and 182:
Page 183 and 184:
Page 185 and 186:
Instruction Execution SequenceWhen
Page 187 and 188:
Instruction Execution SequenceOpera
Page 189 and 190:
Instruction Execution SequenceOpera
Page 191 and 192:
Page 193 and 194:
APPENDIX ACPU Instruction Execution
Page 195 and 196:
ImpliedInstruction :CLC. CLI. CLM.
Page 197 and 198:
ImpliedInstructionR T STiming¢I CP
Page 199 and 200:
ImpliedInstructionBRKTiming00194
Page 201 and 202:
ImmediateInstruction :. L D TTiming
Page 203 and 204:
ImmediateInstructionDIV, MPYTimingr
Page 205 and 206:
DirectInstructionADC, AND, CMP, CPX
Page 207 and 208:
DirectInstructionDIV, MPYTiming~cpu
Page 209 and 210:
Direct Indexed XInstructionADC, AND
Page 211 and 212:
Direct Indexed XInstructionDIV. MPY
Page 213 and 214:
Direct IndirectInstructionADC. AND.
Page 215 and 216:
Direct Indexed X IndirectInstructio
Page 217 and 218:
Direct Indirect Indexed YInstructio
Page 219 and 220:
Direct Indirect LongInstructionADC,
Page 221 and 222:
Direct Indirect Long Indexed YInstr
Page 223 and 224:
AbsoluteInstructionADC, AND, CMP, C
Page 225 and 226:
AbsoluteInstructionDIV, MPYTimingt/
Page 227 and 228:
Absolute BitInstruction : C L B, S
Page 229 and 230:
Absolute Indexed XInstruction : A S
Page 231 and 232:
Absolute Indexed XAbsolute Indexed
Page 233 and 234:
Absolute LongInstructionAD C, AND,
Page 235 and 236:
Absolute LongInstructionJ M PTiming
Page 237 and 238:
Absolute Long Indexed XInstructionD
Page 239 and 240:
Absolute Indirect LongInstructionJ
Page 241 and 242:
StackInstructionPEA. Timing¢CPUAp(
Page 243 and 244:
StackInstructionP H BTiming4tcpuAp(
Page 245 and 246:
StackInstructionPLPTimingAp(cpu)DAT
Page 247 and 248:
StackInstructionPULTimingPSDATA{Cpu
Page 249 and 250:
Direct Bit RelativeInstructionBBG,
Page 251 and 252:
Stack Pointer RelativeInstruction :
Page 253 and 254:
Stack Pointer Relative Indirect Ind
Page 255 and 256:
Block TransferInstructionMVNTimingI
Page 257 and 258:
APPENDIX BSeries MELPS 7700 Machine
Page 259 and 260:
Page 261 and 262:
APPENDIX 8Series MELPS 7700 Machine
Page 263 and 264:
Page 265 and 266:
Page 267 and 268:
Page 269 and 270:
Page 271 and 272:
APPENDIX CSeries MELPS 7700 Instruc
Page 273 and 274:
APPENDIX CSeries MELPS 7700 Instruc
Page 275 and 276:
MITSUBISHI SEMICONDUCTORSMELPS 7700
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