1989_MELPS_7700_Software_Manual

BRK
Force Break
BRK
Operation
PC f- PC + 2
M(S) f- PG
Sf-S-1
M(S) f- PCH
Sf-S-1
M(S) f- PCl
Sf-S-1
M(S) f- PSH
Sf-S-1
M(S) f- PSl
Sf-S-1
I f- 1
PCl f- M(FFFA16)
PCH f- M(FFFB16)
PG f- 0016
Description
When the BRK instruction is executed, the CPU first saves the address where the
next instruction is stored, and then saves the contents of the processor status
register on the stack. Then, the CPU executes a branch to the address in banko
the lower portion of which is specified by the contents of FFFA16 in bank-O and
the upper portion specified by the contents of FFFB16 in bank-O.
Status flags
IPL:
N
V
m
x
D
I
Z
C
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Set to 1.
Not affected.
Not affected.
Addressing mode Syntax Machine code Bytes Cycles
Implied BRK #nn 0016,EA16 2 15
(Note1) The instruction's second byte is ignored, so any value impossible.
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