1989_MELPS_7700_Software_Manual

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APPENDIX 8Series MELPS 7700 Machine InstructionsIMPSymbolImplied addressing modeDescriptionySymbolExclUSive ORDescriptionIMMImmediate addressing modeNegationAAccumulator addressmg modeMovement to the arrow directionDIRDirect addressing modeAceAccumulatorDIR, bDIR, XDirect bit addressmg modeDirect Indexed X addressing modeACCHACCLAccumulator's upper 8 bitsAccumulator's lower 8 bitsDIR, Y(DIR)(DIR, X)(DIR), Yl (DIR)l (DIR), YABSDirect Indexed Y addressing modeDirect indirect addressing modeDirect Indexed X indirect addressing modeDirect Indirect Indexed Y addressing modeDirect indirect long addressing modeDirect indirect long mdexed Y addressing modeAbsolute addressing modeAAHALBBHBLXAccumulator AAccumulator A's upper 8 bitsAccumulator A's lower a bitsAccumulator BAccumulator B's upper 8 bitsAccumulator B's lower 8 bitsIndex register XABS, bABS, XABS, YAbsolute bit addressing modeAbsolute mdexed X addressing modeAbsolute mdexed Y addressing modeXHXLYIndex register X's upper a bitsIndex register X's lower 8 bitsIndex register VABlAbsolute long addressing modeYHIndex register V's upper 8 bitsABl, X(ABS)l(ABS)Absolute long mdexed X addressing modeAbsolute indirect addressing modeAbsolute mdlrect long addressing modeYLSPCIndex register V's lower 8 bitsStack pOinterProgram counter(ABS, X)Absolute mdexed X indirect addressing modePCHProgram counter's upper 8 bitsSTKRElStack addressing modeRelative addressing modePCLPGProgram counter's lower 8 bitsProgram bank registerDIR, b, RElDirect bit relative addressing modeDTData bank registerABS,b,RElAbsolute bit relative addressing modeDPRDirect page registerSRStack pOinter relative addressing modeDPR HDirect page register's upper 8 bits(SR), YBlKCZIoxStack pOinter relative indirect Indexed Y addressingmodeBlock transfer addressing modeCarry flagZero flagInterrupt disable flagDeCimal operation mode flagIndex register length selection flagDPRLPSPSHPS LPSbM(S)Direct page register's lower 8 bitsProcessor status registerProcessor status register's upper 8 bitsProcessor status register's lower 8 bitsProcessor status register's b-th bitContents of memory at address indicated by stackpOinterb-th memory locationmData length selection flagValue of 24-blt address's upper a-bit (A,,-A,,)VOverflow flagValue of 24-bIt address's middle a-bit (A15-A,)NNegative flagValue of 24-blt address's lower a-bit (A,-Ao)IPl+*//\VProcessor Interrupt Priority levelAdditionSubtractionMultiplicationDIVISionLogical ANDLogical OROperation codeNumber of cycleNumber of byteNumber of transfer byte or rotationNumber of registers pushed or pulled265
APPENDIX CSeries MELPS 7700 Instruction Code TableINSTRUCTION CODE TABLE-1~(~HexadeCimal0000 0001 0010 0011 0100 0101 0110 01110 7 ...... 0 4 notation 0 1 2 3 4 5 6 70000 0 BRK0001 1 BPL0010 20011 3 BMIORA ORA SEB ORA ASL ORAA,(DIR,X) A,SR DIR,b , A,DIR DIR A,L(DIR)ORA ORA ORA CLB ORA ASL ORAA,(DIR),Y A,(OIR) A,(SR),Y DIR,b A,DIR,X DIR,X A,LiDIR),YJSR AND JSR AND BBS AND ROL ANDABS A,(DIR,X) ABL A,SR DIR,b,R A,DIR DIR A,L(DIR)AND AND AND BBC AND ROL ANDA,(DIR),Y A,(DIR) A,(SR),Y DIR,b,R A,DIR,X DIR,X A,L(DIR),EOR EOR EOR LSR EOR0100 4 RTI Note 1 MVPA,(DIR,X) A,SR A,DIR DIR A,L(DIR)EOR EOR EOR EOR LSR EOR0101 5 BVC MVNA,(DIR),Y A,(DIR) A,(SR),Y A,DIR,X DIR,X ,LiDIR),YADC ADC LDM ADC ROR ADC0110 6 RTS PERA,(DIR,X) A,SR DIR A.DIR DIR A,L(DIR)0111 7 BVS1000 81001 9 BCC1010 A1011 B BCS1100 CADC ADC ADC LDM ADC ROR ADCA,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X DIR,X A,L(DlR),BRA STA BRA STA STY STA STX STAREL A,(DIR,X) REL A,SR DIR A,DIR DIR A,L(DIR)STA STA STA STY STA STX STAA,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X DIR,Y A,L(DIR),LDY LDA LDX LDA LDY LDA LDX LDAIMM A,(DIR,X) IMM A,SR DIR A,DIR DIR A,L(DIA)LDA LDA LDA LDY LDA LDX LDAA,(DIR),Y A,(OIR) A,(SR)'Y DIR,X A,DIR,X DIR,Y A,L(DIR),YCPY CMP CLP CMP CPY CMP DEC CMPIMM A,(DIR,x) IMM A,SR DIR A,DIR DIR A,L(DIR)CMP CMP CMP CMP DEC CMP1101 D BNE PElA,(DIR),Y A,(DIR) A,(SR),Y A,DIR,X DIR,X A,L(OIR),1110 E,CPX SBC SEP SBC CPX SBC INC SBCIMM A,(DIR,X) IMM A,SR DIR A,DIR DIR A,LiDIR)SBC SBC SBC SBC INC SBC1111 F BEQ PEAA,(DIR),Y A,(DIR) A,(SR),Y A,DIR,X DIR,X A,L(DlR),YNotel: 42,. specifies the contents of the INSTRUCTION CODE TABLE-2,About the second word's codes, refer to the INSTRUCTION CODE TABLE-2Note 2 : 89,. specifies the contents of the INSTRUCTION CODE TABLE-3About the third word's codes, refer to the INSTRUCTION CODE TABLE-21000 1001 1010 1011 1100 1101 11108 9 A B C D EORA DEC CLB ORA ASL ORACLCTASA,ABS,Y A ABS,b A,ABS,X ABS,X A,ABL,XAND INC BBC AND ROL ANDSECTSAA,ABS,Y A ABS,b,R A,ABS,X ABS,X A,ABL,XEOR JMP EOR LSRCLI PHY TADA,ABS,Y ABL A,ABS,X ABS,XADC JMP ADC ROR ADCSEI PLY TDAA,ABS,Y(ABS,X) A,ABS,X ABS,X A,ABL,XDEY Note 2 TXA PHTSTY STA STXABS A,ABS ABSSTA LDM STA LDMTYA TXS TXYA,ABS,Y ABS A,ABS,X ABS,XLDA LDY LDA LDXTAY TAX PLTA,IMM ABS A,ABS ABSLDA LDY LDA LOX LDACLV TSX TYXA,ABS,YABS,X A,ABS,X ABS,Y A,ABL,XCMP CPY CMP DECINY DEX WITA,IMM ABS A,ABS ABSCMP JMP CMP DEC CMPCLM PHX STPA,ABS,YL(ABS) A,ABS,X ABS,X A,ABL,XSBC CPX SBC INCINX NOP PSHA,IMM ABS A,ABS ABS1111ORA ASL SEB ORA ASL ORAPHPPHDA,IMM A ABS,b A,ABS ABS A,ABLAND ROL BBS AND ROL ANDPLPPLDA,IMM A ABS,b,R A,ABS ABS A,ABLEOR LSR JMP EOR LSR EORPHAPHGA,IMM A ABS A,ABS ABS A,ABLSBC JSR SBC INC SBCSEM PLX PULA,ABS,Y(ABS,X) A,ABS,X ABS,X A,ABL,XFEORA,ABL,XADC ROR JMP ADC ROR ADCPLARTLA,IMM A (ABS) A,ABS ABS A,ABLSTAA,ABLSTAA,ABL,XLDAA,ABLCMPA,ABLSBCA,ABL266
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MITSUBISHI SEMICONDUCTORSMELPS 7700
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ContentsContents1. Introduction of
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Register Configuration2. Register C
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Register Configuration2.4 Stack Poi
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Register Configuration2.9 Processor
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Addressing Modes3. Addressi ng Mode
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ImmediateModeFunctionImmediate addr
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DirectModeFunctionDirect addressing
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Direct Indexed XModeFunctionDirect
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Direct Indexed YModeFunctionDirect
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D;,rect Indexed X IndirectModeFunct
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Direct Indexed X Indirectex.: Mnemo
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Direct Indirect Indexed Yex.: Mnemo
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Direct Indirect LongModeFunctionDir
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Direct Indirect Long Indexed Yex.:
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AbsoluteModeFunctionAbsolute addres
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Absolute BitModeFunctionAbsolute bi
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Absolute Indexed Xex.: MnemonicAOC
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Absolute Indexed Yex.: MnemonicLOX
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Absolute Long Indexed XModeFunction
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Absolute Indirect LongModeFunctionI
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StackModeFunctionStack addressing m
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RelativeModeFunctionRelative addres
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Direct Bit Relativeex.: Mnemonic Ma
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Absolute Bit Relativeex. : Mnemonic
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Stack Pointer Relative Indirect Ind
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Block TransferModeFunctionBlock tra
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Instructions4. Instructions4.1 Inst
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Instructions4.1.2 Arithmetic Instru
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InstructionsCategory Instruction De
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InstructionsThe table below lists t
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AND logical AND ANDOperation Acc f-
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BBC Branch on Bit Clear BBCOperatio
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BeeBranch on Carry ClearBeeOperatio
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BEQBranch on EqualBEQOperationWhen
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BNEBranch on Not EqualBNEOperationW
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BRABranch AlwaysBRAOperationFor sho
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eveBranch on Overflow CleareveOpera
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CLBClear BitCLBOperationM (- MA IMM
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,Cli Clear Interrupt Disable Status
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CLPClear Processor StatusCLPOperati
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CMP Compare CMPOperationAcc - MDesc
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CpyCompare Memory and Index Registe
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DEXDecrement Index Register X by On
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DIV Divide DIVOperationB(remainder}
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EOR Exclusive OR Memory with Accumu
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INX Increment Index Register X by O
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JMPJumpJMPOperationIf absolute addr
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LOA Load Accumulator from Memory LO
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LOT Load Immediate to Data Bank Reg
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LOYLoad Index Register Y from Memor
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MPYMultiplyMPYOperationB, A b A x M
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MVP Move Positive MVPOperationMn-k
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ORA OR Memory with Accumulator ORAO
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PElPush Effective Indirect AddressP
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PHAPush Accumulator A on StackPHAOp
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PHDOperationPush Direct Page Regist
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PHPPush Processor Status on StackPH
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PHXPush Index Register X on StackPH
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PLAPull Accumulator A from StackPLA
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PLDOperationPull Direct Page Regist
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PLTPull Data Bank Register from Sta
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PLYPull Index Register Y from Stack
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PSHPushPSHM(8) f- OPRH8 f- 8-1M(8)
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PULPullPULSf- S+1PSL f- M(S)Sf- S+1
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ROL Rotate One Bit Left ROLOperatio
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RTIReturn from InterruptRTIOperatio
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RTSReturn from SubroutineRTSOperati
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SEBSet BitSEBOperationM f- M V IMMI
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SEI Set Interrupt Disable Status SE
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SEPSet Processor StatusSEPOperation
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STPStopSTPOperationDescriptionStop
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STYStore Index Register Y in Memory
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lASTransfer Accumulator A to Stack
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TAYTransfer Accumulator A to Ind~x
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TBSTransfer Accumulator B to Stack
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TBvTransfer Accumulator B to Index
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TOBTransfer Direct Page Register to
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TSBTransfer Stack Pointer to Accumu
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TXATransfer Index Register X to Acc
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TXSTransfer Index Register X to Sta
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TVATransfer Index Register Y to Acc
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TYXTransfer Index Register Y to XTY
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XABExchange Accumulator A and 8XABO
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Notes for Programming(11) The code
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Instruction Execution Sequence6.2 C
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Instruction Execution SequenceIE)·
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Instruction Execution Sequence{Exam
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Instruction Execution Sequence(Exam
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Instruction Execution SequenceWhen
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Instruction Execution SequenceOpera
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Instruction Execution SequenceOpera
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APPENDIX ACPU Instruction Execution
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ImpliedInstruction :CLC. CLI. CLM.
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ImpliedInstructionR T STiming¢I CP
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ImpliedInstructionBRKTiming00194
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ImmediateInstruction :. L D TTiming
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ImmediateInstructionDIV, MPYTimingr
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DirectInstructionADC, AND, CMP, CPX
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DirectInstructionDIV, MPYTiming~cpu
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Direct Indexed XInstructionADC, AND
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Direct Indexed XInstructionDIV. MPY
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Direct IndirectInstructionADC. AND.
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Direct Indexed X IndirectInstructio
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Direct Indirect Indexed YInstructio
Page 219 and 220: Direct Indirect LongInstructionADC,
Page 221 and 222: Direct Indirect Long Indexed YInstr
Page 223 and 224: AbsoluteInstructionADC, AND, CMP, C
Page 225 and 226: AbsoluteInstructionDIV, MPYTimingt/
Page 227 and 228: Absolute BitInstruction : C L B, S
Page 229 and 230: Absolute Indexed XInstruction : A S
Page 231 and 232: Absolute Indexed XAbsolute Indexed
Page 233 and 234: Absolute LongInstructionAD C, AND,
Page 235 and 236: Absolute LongInstructionJ M PTiming
Page 237 and 238: Absolute Long Indexed XInstructionD
Page 239 and 240: Absolute Indirect LongInstructionJ
Page 241 and 242: StackInstructionPEA. Timing¢CPUAp(
Page 243 and 244: StackInstructionP H BTiming4tcpuAp(
Page 245 and 246: StackInstructionPLPTimingAp(cpu)DAT
Page 247 and 248: StackInstructionPULTimingPSDATA{Cpu
Page 249 and 250: Direct Bit RelativeInstructionBBG,
Page 251 and 252: Stack Pointer RelativeInstruction :
Page 253 and 254: Stack Pointer Relative Indirect Ind
Page 255 and 256: Block TransferInstructionMVNTimingI
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Page 261 and 262: APPENDIX 8Series MELPS 7700 Machine
Page 269: APPENDIX BSeries MELPS 7700 Machine
Page 273 and 274: APPENDIX CSeries MELPS 7700 Instruc
Page 275 and 276: MITSUBISHI SEMICONDUCTORSMELPS 7700
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