Tech Hardware Supply Chain - Gazhoo

Bhavin Shah
(852) 2800-8538
bhavin.a.shah@jpmorgan.com
Ashable hardmasks are layers
used along with photoresist to
serve as the mask for etch
processes in cases where the
use of photoresist alone is not
adequate.
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Asia Pacific Equity Research
20 April 2009
produces a relatively limited number of designs, we expect foundries to widely adopt
immersion lithography for critical layers at 45nm and possibly at sub-65nm half step
designs (i.e., ~55nm).
Immersion side-effects: Increased defect inspection
Immersion lithography has introduced new potential sources of defects into chip
fabrication. In order to increase the effective numerical aperture of a leading-edge
lithography system, water, which provides a magnifying effect, instead of air, fills
the space between the bottom of the lens and the surface of the wafer. Water actually
comes into contact with the wafer’s surface, increasing the potential of defects
occurring as well as possibly transporting particles from the wafer’s edge onto the
surface of the wafer where the devices are formed, resulting in an increased risk of
“killer defects” (i.e. unwanted particles that result in device failure).
Examples of immersion lithography-specific defects are shown in Figure 195 below.
This new source of device-killing particles require a higher level of defectmonitoring
to ensure that yield levels remain high. Defect control is usually quoted
as the major issue in the successful ramp of device yields using immersion
lithography. The bottom line: frequent change in advanced lithography is one of the
major drivers of increased process control usage.
Figure 195: Examples of immersion lithography specific defects
Source: Yield Management Solutions and Company reports.
Increasing complexity requires more use of process control to keep yields high
An increase in complexity drives the need for more aggressive or more stringent
design rules, which makes high-yield chip fabrication more difficult as there is less
leeway or error budget in the manufacturing process. The resulting level of the
combined variation in overlay and CD (critical dimension) uniformity will be higher
(worse), prompting higher sampling frequency (i.e. a higher level of process control
sampling rates). As a result, there will be greater use of patterning-related process
control including photo-mask inspection, overlay metrology and optical CD
metrology.
CVD layers are increasingly used to assist lithography
Ashable hard masks and antireflective coatings have been adopted in the
manufacturing of NAND flash chips for certain critical applications such as shallow
trench isolation (STI), gate etch and contact etch. These films offer high selectivity to
the material being etched and therefore enable enhanced profile control (i.e., vertical
walls) when etching high aspect ratio features, even as the thickness of the patterned
photoresist continues to thin. The number of process steps that use these films will
first increase in NAND flash and also grow beyond flash as these films/processes are
adopted in DRAM and logic applications as well.