Workshopband als PDF - Mpc.belwue.de

MPC-WORKSHOP FEBRUAR 2013
Design and Implementation of a Mixed-Signal ASIC in
Ultra-Thin CMOS Technology for 2-D Stress
Measurement
Abstract—A CMOS sensor for in-plane stress
measurement is presented. The device is designed
using the IMS 0.5 µm CMOS Gate Array technology
and it is to be fabricated as a flexible chip using
the Chipfilm TM technology of IMS CHIPS. The
sensor consists of four channels, each of which
includes a sensor core, a readout circuit, and a 10bit
analog-to-digital converter (ADC). The linearity
of the sensor is enhanced by the design of the sensor
core and readout. The readout is designed to be
insensitive to the induced stress in order to maintain
proper operation at all times. The internal
sensor timing can be tuned through a serial interface
for adjusting the analog performance of the
sensor.
Index Terms—Stress sensor, ultra-thin chip, flexible
chip, stress-insensitive mixed-signal design
I. INTRODUCTION
Flexible electronics is a contemporary technology
that is likely to grow rapidly in near future. The hybrid
system-in-foil (SiF) devices, that house an ultra-thin
chip, are expected to be an important part of the market
[1]. By using the properties of the ultra-thin chips,
stress on a surface can be measured or topological
information can be acquired from the adjacent surface.
The piezoresistive effect in silicon is a well explained
phenomenon which is widely used for stress
sensing. Resistors or MOSFET’s are used as sensing
elements. The information is obtained by measuring
the stress induced variation in resistance and mobility
for resistors and MOSFET’s respectively. The choice
differs according to the final application of the sensor.
In literature, a number of studies are available and the
target applications cover various topics such as dental
care, wire bonding, flip chip bonding, and wafer stability
[2]-[6].
In this work, a sensor is designed for measuring the
in-plane stress or the flex on a bendable surface. Due
to the extremely low thickness of the device, the rigid-
Yigit U. Mahsereci, mahsereci@ims-chips.de, and Cor Scherjon,
scherjon@ims-chips.de are with Institut für Mikroelektronik
Stuttgart, Allmandring 30a, 70569 Stuttgart.
Yigit U. Mahsereci, Cor Scherjon
Figure 1: Ultra-thin (thickness < 20 µm) silicon chip. The chip is
fabricated with Chipfilm TM technology of IMS CHIPS [10].
ity of the silicon is negligible; therefore the data of the
surface state can be harvested without distortion. Despite
the physical advantage, ultra-thin chips have
intrinsic problems that are to be taken care of such as,
substantial stress in the devices and vulnerability to
thermal variations due to low heat capacity. Also, the
out-of-plane stress component must be eliminated so
that in-plane data is not corrupted. The readout circuit
is designed to be insensitive to stress, thermal fluctuations
and the out-of-plane stress component. The sensor
provides 10-bit digital output for four different
stress sensitive MOSFET pairs. The enhanced linearity
of the sensor makes it possible to accurately calculate
the 2-D polar coordinates of the stress vector.
II. GATEFOREST TM TECHNOLOGY
The IMS CHIPS GateForest TM technology provides
key features such as quick fabrication cycle, mixedsignal
integration, on-chip RAMs at a process node of
0.8 µm or 0.5 µm CMOS technology [7], [8]. Various
standard die sizes, so-called master chips are offered.
Each master includes a different number of digital and
analog core cells, which enables mixed-signal integration.
All wafers are already processed until the metallization
and are residing in the foundry. By processing
different metallization layers on top of the preprocessed
master wafers, different customer-specific
designs can be realized. Hence, the complete process
cycle is reduced to only back-end-of-line. Therefore,
even small volume fabrications can be made in a lowcost
manner.
7