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IV. IMPLEMENTATION
The implementation on the Spartan 3E board was
done by testing the receiver structure at one time and
the transmitter with the clock blocks on another to
simplify it. The set up used can be seen on Figure 5,
the middle board is only used for easier access to the
pins while the board on the right correspond to the
microcontroller used.
Some minor changes were made in the code, particularly
for the receptor, in the amount of inputs and
outputs of the structures due to a limited number
available on the board. Some multiplexers were implemented
to have a bigger number of outputs available
and some intermediate signals where routed out
in order to have a better understanding of the performance
of the code. The *.ucf files were done for the
allocation of the pins accordingly.
V. CONCLUSION
The desired VHDL code was designed and simulated;
it was also synthesized and implemented on a
Spartan 3E Board. The system was tested and was
able to receive and transmit USB packets. It has also
both, the capability to send SOF packets to play host if
requested as well as calculate or manipulate the CRCs
for almost every packet. The received information was
saved and able to be read out when the user decides to.
After further testing the manufacturing of an ASIC
should be possible.
AKNOWLEDGEMENT
The author would like to thank Prof. Dr.-Ing. Walter
Ludescher for his advice and guidance during the
development of this project, as well as for the microcontroller
program used for testing.
REFERENCES
[1] I. Xilinx, Spartan-3 Libraries Guide for HDL, 2008.
[2] H. P. I. L. M. Compaq, Universal Serial Bus Specification
Revision 2.0, 2000.
56
VHDL BASED CIRCUIT DESCRIPTION TO TRANSMIT,
RECEIVE AND ANALYSE USB DATA PACKETS
María Guadalupe Salgado Suárez obtained
the academic degree B. Sc. in mechatronics
engineering at the Monterrey Institute of
Technology and Higher Education in Mexico
in December 2009. She then continued her
master studies in electrical engineering at the
University of Applied Sciences Ravensburg-
Weingarten, having received the M. Eng.
degree in March 2013. This publication is
part of her Master Thesis.